Timing margins for on-chip variations from sensitivity data
View Patent ↗An approach is provided in which a system executes transistor-level circuit simulation of a standard cell that includes parameters corresponding to a semiconductor manufacturing technology process. Sensitivity data is collected that quantifies changes to performance metrics corresponding to the standard cell in response to adjusting one or more of the parameters during the transistor-level circuit simulation. In turn, the system generates derate factors based upon the sensitivity data and tests an integrated circuit design according to the derate factors. Testing the integrated circuit design includes performing static timing analysis on the integrated circuit design that simulates operation of a device built from the integrated circuit design using the semiconductor technology process. In one embodiment, when the static timing analysis indicates timing violations, the system dynamically generates custom derate factors for particular cell instances corresponding to the timing violations. In turn, subsequent timing analysis is performed using the custom derate factors.
1. A method comprising:
executing, by one or more processors, transistor-level circuit simulation of a standard cell included in a cell library, wherein the standard cell includes one or more parameters corresponding to a semiconductor manufacturing technology process;
collecting, by one or more of the processors, sensitivity data that quantifies one or more changes to one or more performance metrics corresponding to the standard cell in response to adjusting one or more of the parameters during the transistor-level circuit simulation;
generating, by one or more of the processors, one or more derate factors based upon the sensitivity data;
retrieving, from a storage area by one or more of the processors, an integrated circuit design that includes one or more cell instances of the standard cell; and
testing the integrated circuit design utilizing the one or more derate factors, wherein the testing comprises a static timing analysis of the integrated circuit design.
2. The method of claim 1 further comprising:
creating, from the sensitivity data, one or more sensitivity tables that correspond to the standard cell, wherein each of the one or more sensitivity tables correspond to one or more timing arcs and a plurality of load-slew combinations.
3. The method of claim 2 wherein the static timing analysis simulates operation, utilizing one or more of the sensitivity tables, of an integrated circuit built from the integrated circuit design using the semiconductor manufacturing technology process.
4. The method of claim 3 further comprising:
retrieving a first set of arc sensitivity values from the one or more sensitivity tables corresponding to a first one of the plurality of load-slew combinations;
creating an advanced on-chip variation (AOCV) table based upon the retrieved first set of arc sensitivity values, wherein the AOCV table includes one or more first derate factors computed from the first set of arc sensitivity values; and
simulating a first instance of the standard cell included in the integrated circuit design utilizing one or more of the first derate factors during the static timing analysis.
5. The method of claim 4 wherein the integrated circuit design includes a second instance of the standard cell, the method further comprising:
utilizing, during the static timing analysis, one or more of the first derate factors to simulate the second instance of the standard cell included in the integrated circuit design;
detecting a timing violation at the second instance of the standard cell;
retrieving a second set of arc sensitivity values from the one or more sensitivity tables, wherein the second set of arc sensitivity tables corresponds to a second one of the plurality of load-slew combinations that is different than the first load-slew combination;
determining one or more second derate factors based upon the second set of arc sensitivity values; and
utilizing one or more of the second derate factors to simulate the second instance of the standard cell during a subsequent static timing analysis of the integrated circuit design.
6. The method of claim 5 wherein the subsequent static timing analysis utilizes one or more of the first derate factors to simulate the first instance of the standard cell concurrently with utilizing one or more of the second derate factors to simulate the second instance of the standard cell.
7. The method of claim 5 further comprising:
analyzing the timing violation during the simulation;
identifying an actual load-slew combination of the second instance of the standard cell, wherein the actual load-slew combination includes an output load and an input slew of the second instance of the standard cell;
comparing the actual load-slew combination with the plurality of load-slew combinations; and
selecting the second load-slew combination in response to the comparison.
8. The method of claim 1 further comprising:
retrieving technology-specific statistical parameters from a storage area, wherein the technology-specific statistical parameters correspond to a different semiconductor manufacturing technology process; and
utilizing the technology-specific statistical parameters during the transistor-level circuit simulation to generate the sensitivity data.
9. An information handling system comprising:
one or more processors;
one or more memories accessible by at least one of the processors;
a characterization module executing on one of the processors that executes transistor-level circuit simulation of a standard cell included in a cell library, wherein the standard cell includes one or more parameters corresponding to a semiconductor manufacturing technology process;
collection logic included in the characterization module that collects sensitivity data, wherein the sensitivity data quantifies one or more changes to one or more performance metrics corresponding to the standard cell in response to adjusting one or more of the parameters during the transistor-level circuit simulation;
a derate factor generation module executing on one of the processors that generates one or more derate factors based upon the sensitivity data; and
a testing module executing on one of the processors that retrieves an integrated circuit design from one of the memories and tests the integrated circuit design utilizing the one or more derate factors, wherein the integrated circuit design includes one or more cell instances of the standard cell, and wherein the testing comprises a static timing analysis of the integrated circuit design.
10. The information handling system of claim 9 further comprising:
sensitivity table generation logic included in the characterization module that creates, from the sensitivity data, one or more sensitivity tables that correspond to the standard cell, wherein each of the one or more sensitivity tables correspond to one or more timing arcs and a plurality of load-slew combinations.
11. The information handling system of claim 10 wherein the static timing analysis simulates operation, utilizing one or more of the sensitivity tables, of an integrated circuit built from the integrated circuit design using the semiconductor manufacturing technology process.
12. The information handling system of claim 11 further comprising:
retrieval logic included in the derate factor generation module that retrieves a first set of arc sensitivity values from the one or more sensitivity tables corresponding to a first one of the plurality of load-slew combinations;
advanced on-chip variation (AOCV) table creation logic included in the derate factor generation module that creates an AOCV table based upon the retrieved first set of arc sensitivity values, wherein the AOCV table includes one or more first derate factors computed from the first set of arc sensitivity values; and
wherein the testing module utilizes, during the static timing analysis, one or more of the first derate factors to simulate a first instance of the standard cell included in the integrated circuit design.
13. The information handling system of claim 12 wherein the integrated circuit design includes a second instance of the standard cell, the information handling system further comprising:
utilization logic included in the testing module that utilizes, during the static timing analysis, one or more of the first derate factors to simulate the second instance of the standard cell included in the integrated circuit design;
detection logic included in the testing module that detects a timing violation at the second instance of the standard cell;
the retrieval logic that retrieves a second set of arc sensitivity values from the one or more sensitivity tables, wherein the second set of arc sensitivity tables corresponds to a second one of the plurality of load-slew combinations that is different than the first load-slew combination;
determination logic included in the derate factor generation module that determines one or more second derate factors based upon the second set of arc sensitivity values; and
the utilization logic that utilizes one or more of the second derate factors to simulate the second instance of the standard cell during a subsequent static timing analysis of the integrated circuit design.
14. The information handling system of claim 13 wherein the subsequent static timing analysis utilizes one or more of the first derate factors to simulate the first instance of the standard cell concurrently with utilizing one or more of the second derate factors to simulate the second instance of the standard cell.
15. The information handling system of claim 13 further comprising:
analysis logic included in the testing module that analyzes the timing violation during the static timing analysis;
identification logic included in the testing module that identifies an actual load-slew combination of the second instance of the standard cell, wherein the actual load-slew combination includes an output load and an input slew of the second instance of the standard cell;
comparison logic included in the derate factor generation module that compares the actual load-slew combination with the plurality of load-slew combinations; and
selection logic included in the derate factor generation module that selects the second load-slew combination in response to the comparison.
16. A computer program product stored in a computer readable storage medium, comprising computer program code that, when executed by an information handling system, causes the information handling system to perform actions comprising:
executing transistor-level circuit simulation of a standard cell included in a cell library, wherein the standard cell includes one or more parameters corresponding to a semiconductor manufacturing technology process;
collecting sensitivity data that quantifies one or more changes to one or more performance metrics corresponding to the standard cell in response to adjusting one or more of the parameters during the transistor-level circuit simulation;
generating one or more derate factors based upon the sensitivity data;
retrieving, from a storage area, an integrated circuit design that includes one or more cell instances of the standard cell; and
testing the integrated circuit design utilizing the one or more derate factors, wherein the testing comprises a static timing analysis of the integrated circuit design.
17. The computer program product of claim 16 wherein the computer readable storage medium stores additional instructions that, when executed by the information handling system, cause the information handling system to perform additional actions comprising:
creating, from the sensitivity data, one or more sensitivity tables that correspond to the standard cell, wherein each of the one or more sensitivity tables correspond to one or more timing arcs and a plurality of load-slew combinations.
18. The computer program product of claim 17 wherein the static timing analysis simulates operation, utilizing one or more of the sensitivity tables, of an integrated circuit built from the integrated circuit design using the semiconductor manufacturing technology process.
19. The computer program product of claim 18 wherein the computer readable storage medium stores additional instructions that, when executed by the information handling system, cause the information handling system to perform additional actions comprising:
retrieving a first set of arc sensitivity values from the one or more sensitivity tables corresponding to a first one of the plurality of load-slew combinations;
creating an advanced on-chip variation (AOCV) table based upon the retrieved first set of arc sensitivity values, wherein the AOCV table includes one or more first derate factors computed from the first set of arc sensitivity values; and
simulating a first instance of the standard cell included in the integrated circuit design utilizing one or more of the first derate factors during the static timing analysis.
20. The computer program product of claim 19 wherein the integrated circuit design includes a second instance of the standard cell, and wherein the computer readable storage medium stores additional instructions that, when executed by the information handling system, cause the information handling system to perform additional actions comprising:
utilizing, during the static timing analysis, one or more of the first derate factors to simulate the second instance of the standard cell included in the integrated circuit design;
detecting a timing violation at the second instance of the standard cell;
retrieving a second set of arc sensitivity values from the one or more sensitivity tables, wherein the second set of arc sensitivity tables corresponds to a second one of the plurality of load-slew combinations that is different than the first load-slew combination;
determining one or more second derate factors based upon the second set of arc sensitivity values; and
utilizing one or more of the second derate factors to simulate the second instance of the standard cell during a subsequent static timing analysis of the integrated circuit design.