Manufacturing methods for laterally diffused metal oxide semiconductor devices
View Patent ↗Fabrication processes for semiconductor devices are presented here. The device includes a support substrate, a buried oxide layer overlying the support substrate, a first semiconductor region located above the buried oxide layer and having a first conductivity type. The device also includes second, third, fourth, and fifth semiconductor regions. The second semiconductor region is located above the first semiconductor region, and it has a second conductivity type. The third semiconductor region is located above the second semiconductor region, and it has the first conductivity type. The fourth semiconductor region is located above the third semiconductor region, and it has the second conductivity type. The fifth semiconductor region extends through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and it has the second conductivity type.
1. A method of fabricating a semiconductor device on a semiconductor-on-insulator substrate comprising a support layer, a buried insulator layer overlying the support layer, and a layer of semiconductor material overlying the buried insulator layer, the method comprising:
forming epitaxially grown semiconductor material overlying the layer of semiconductor material, the epitaxially grown semiconductor material having a first conductivity type, and at least a portion of the epitaxially grown semiconductor material serving as a first semiconductor region of the semiconductor device;
forming a second semiconductor region in the epitaxially grown semiconductor material, the second semiconductor region located above the first semiconductor region and having a second conductivity type;
forming a third semiconductor region in the epitaxially grown semiconductor material, the third semiconductor region located above the second semiconductor region and having the first conductivity type;
forming a fourth semiconductor region in the epitaxially grown semiconductor material, the fourth semiconductor region located above the third semiconductor region and having the second conductivity type; and
forming a fifth semiconductor region in the epitaxially grown semiconductor material, the fifth semiconductor region extending through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and having the second conductivity type.
2. The method of claim 1 , wherein forming the epitaxially grown semiconductor material comprises:
forming a first layer of epitaxially grown semiconductor material overlying the layer of semiconductor material; and
forming a second layer of epitaxially grown semiconductor material overlying the first layer of epitaxially grown semiconductor material; wherein
the second semiconductor region is formed in the first layer of epitaxially grown semiconductor material before forming the second layer of epitaxially grown semiconductor material; and
the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are formed in the second layer of epitaxially grown semiconductor material.
3. The method of claim 1 , further comprising forming a semiconductor contact region in the fifth semiconductor region, the semiconductor contact region having the second conductivity type, wherein the fifth semiconductor region electrically couples the second semiconductor region to the semiconductor contact region.
4. A method of fabricating a semiconductor device, the method comprising:
forming a layer of additional semiconductor material overlying a layer of semiconductor material of a semiconductor-on-insulator substrate, wherein the semiconductor-on-insulator substrate comprises a support layer, a buried insulator layer overlying the support layer, and the layer of semiconductor material overlying the buried insulator layer, and wherein the layer of additional semiconductor material comprises a first semiconductor region having a first conductivity type;
forming a second semiconductor region located in the additional semiconductor material and having a second conductivity type;
forming a third semiconductor region located in the additional semiconductor material above the second semiconductor region and having the first conductivity type;
forming a fourth semiconductor region located in the additional semiconductor material above the third semiconductor region and having the second conductivity type;
forming a fifth semiconductor region located in the additional semiconductor material above the second semiconductor region and having the second conductivity type, the fifth semiconductor region being adjacent to both the third semiconductor region and the fourth semiconductor region; and
forming a sixth semiconductor region located in the additional semiconductor material adjacent to the fourth semiconductor region and having the first conductivity type, wherein no portion of the second semiconductor region is located under the sixth semiconductor region.
5. The method of claim 4 , further comprising:
forming a semiconductor contact region located in the fifth semiconductor region, and having the second conductivity type, wherein the fifth semiconductor region electrically couples the second semiconductor region and the fourth semiconductor region to the semiconductor contact region.
6. The method of claim 4 , further comprising:
forming a semiconductor contact region located in the sixth semiconductor region and having the second conductivity type.
7. The method of claim 4 , further comprising:
forming a gate structure that overlies a portion of the fourth semiconductor region and overlies a portion of the sixth semiconductor region, wherein:
the fifth semiconductor region serves as a drain region of a transistor;
the sixth semiconductor region serves as a source region of the transistor; and
the gate structure serves as the gate of the transistor.
8. A method of fabricating a semiconductor device on a substrate having a support layer, a buried oxide layer overlying the support layer, and a first semiconductor region located above the buried oxide layer and having a first conductivity type, the method comprising:
forming a second semiconductor region located above the first semiconductor region and having a second conductivity type;
forming a third semiconductor region located above the second semiconductor region and having the first conductivity type;
forming a fourth semiconductor region located above the third semiconductor region and having the second conductivity type;
forming a fifth semiconductor region extending through the fourth semiconductor region and the third semiconductor region to the second semiconductor region, and having the second conductivity type; and
forming a sixth semiconductor region located in the additional semiconductor material adjacent to the fourth semiconductor region and having the first conductivity type, wherein no portion of the second semiconductor region is located under the sixth semiconductor region.
9. The method of claim 8 , further comprising:
epitaxially growing an epitaxial semiconductor material located above the buried oxide layer, wherein:
the first semiconductor region comprises a portion of the epitaxially grown semiconductor material; and
the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are all located in the epitaxially grown semiconductor material.
10. The method of claim 8 , further comprising:
forming a semiconductor contact region located in the fifth semiconductor region and having the second conductivity type, wherein the fifth semiconductor region electrically couples the second semiconductor region to the semiconductor contact region.
11. A method of fabricating a semiconductor device on a semiconductor-on-insulator substrate having a support layer, a buried insulator layer overlying the support layer, and a layer of semiconductor material overlying the buried insulator layer, the method comprising:
forming a first layer of additional semiconductor material overlying the layer of semiconductor material, the first layer of additional semiconductor material having a first conductivity type;
forming an implant region in the first layer of additional semiconductor material, the implant region having the first conductivity type;
forming a second semiconductor region in the first layer of additional semiconductor material and above the implant region, the second semiconductor region having a second conductivity type;
forming a second layer of additional semiconductor material overlying the first layer of additional semiconductor material, the second layer of additional semiconductor material having the first conductivity type;
forming a third semiconductor region in the second layer of additional semiconductor material and above the second semiconductor region, the third semiconductor region having the first conductivity type;
forming a fourth semiconductor region in the second layer of additional semiconductor material and above the third semiconductor region, the fourth semiconductor region having the second conductivity type; and
forming a fifth semiconductor region in the second layer of additional semiconductor material and extending through the third semiconductor region, through the fourth semiconductor region, and to the second semiconductor region, the fifth semiconductor region having the second conductivity type.
12. The method of claim 11 , further comprising:
forming a sixth semiconductor region around and adjacent to the fourth semiconductor region, the sixth semiconductor region having the first conductivity type.
13. The method of claim 12 , wherein forming the sixth semiconductor region comprises forming the sixth semiconductor region in the second layer of semiconductor material.
14. The method of claim 12 , further comprising:
forming a gate structure that bridges the fourth semiconductor region and the sixth semiconductor region.
15. The method of claim 14 , wherein forming the gate structure comprises forming a ring-shaped gate insulator and a ring-shaped gate electrode.
16. The method of claim 14 , further comprising:
forming semiconductor contact regions in the fifth semiconductor region and in the sixth semiconductor region.
17. The method of claim 16 , wherein forming the semiconductor contact regions comprises forming the semiconductor contact regions in the second layer of additional semiconductor material.
18. The method of claim 17 , wherein forming the semiconductor contact regions comprises implanting ions into the fifth semiconductor region and into the sixth semiconductor region.
19. The method of claim 17 , wherein forming the semiconductor contact regions comprises forming source, drain, and body implants for the semiconductor device.