IP Library Granted Patent US 8,809,078
Granted Patent B1
US 8,809,078 · App. 13/766,771 · Granted Aug 19, 2014

Solar powered IC chip

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Quick Facts
Patent No.
US 8,809,078
App. No.
13/766,771
Granted
Aug 19, 2014
Kind
B1
Abstract

A self-powered circuit package includes a substrate and an integrated circuit (IC). The IC is mounted on a surface of the substrate. An electrical interconnector electrically couples the IC to the substrate. A solar cell is provided having opposing first and second main surfaces. A portion of the first main surface of the solar cell is configured to receive light from an external source. The solar cell converts energy of the received light into electrical power. The solar cell is disposed above the IC and electrically connected to the IC by way of the substrate to supply the generated power to the IC. A clear mold compound encapsulates a surface of the substrate, the IC, the electrical interconnector, and the solar cell.

Claims (32)

1. A self-powered integrated circuit (IC) package, comprising:

a substrate having opposing first and second main surfaces;

an integrated circuit (IC) chip having opposing first and second main surfaces, the second main surface of the IC chip being mounted on the first main surface of the substrate;

at least one first electrical interconnector that electrically couples the IC chip to the substrate;

a solar cell having opposing first and second main surfaces, at least a portion of the first main surface of the solar cell being configured to receive light from an external source, the solar cell being configured to convert energy of the received light into electrical power;

a plurality of second electrical interconnectors electrically coupling the solar cell to the first main surface of the substrate and thereby electrically connecting the solar cell to the IC chip via the substrate to supply the generated electrical power thereto, wherein the solar cell extends over the first main surface of the IC chip, and is mounted and electrically connected to the first main surface of the substrate with solder balls; and

a mold compound disposed on the first main surface of the substrate and which encapsulates the IC chip, the at least one first electrical interconnector, and at least a portion of the solar cell.

2. The package of claim 1 , wherein the mold compound is transparent or transmissive to at least a wavelength of the received light, and the first main surface of the solar cell is encapsulated by the mold compound.

3. The package of claim 1 , further comprising a spacer located between the first main surface of the IC chip and the second main surface the solar cell, wherein the solar cell is mounted on the first main surface of the IC chip by way of the spacer.

4. The package of claim 1 , wherein the second electrical interconnectors comprise bond wires.

5. The package of claim 1 , wherein a surface area of the first main surface of the solar cell is larger than a surface area of the first main surface of the IC chip.

6. The package of claim 1 , further comprising a plurality of solder balls mounted to the second main surface of the substrate.

7. The package of claim 1 , further comprising an encapsulant laminated on at least the light receiving portion of the first main surface of the solar cell, wherein the encapsulant is transparent or transmissive to at least a wavelength of the received light.

8. The package of claim 7 , wherein the laminated portion of the first main surface of the solar cell is also laminated with glass.

9. The package of claim 7 , wherein at least the laminated portion of the first main surface of the solar cell is exposed through the mold compound.

10. The package of claim 1 , wherein the IC chip is attached to the substrate with an adhesive.

11. The package of claim 10 , wherein the at least one first electrical interconnector comprises a plurality of bond wires.

12. A self-powered integrated circuit (IC) package, comprising:

a substrate having opposing first and second main surfaces;

an integrated circuit (IC) chip having opposing first and second main surfaces, the second main surface of the IC chip being mounted on and electrically connected to the first main surface of the substrate;

a solar cell having opposing first and second main surfaces, at least a portion of the first main surface of the solar cell being configured to receive light from an external source, wherein the solar cell converts energy of the received light into electrical power, wherein the second main surface of the solar cell is in facing arrangement with the first main surface of the IC chip;

a first plurality of solder balls for attaching and electrically connecting the solar cell to the first main surface of the substrate and thereby electrically connecting the solar cell to the IC chip via the substrate to supply the generated electrical power thereto, wherein the solar cell extends over the first main surface of the IC chip; and

a mold compound that encapsulates at least portions of the first main surface of the substrate, the IC chip and the solar cell.

13. The package of claim 12 , wherein the mold compound is transparent or transmissive to at least a wavelength of the received light, and the first main surface of the solar cell is encapsulated by the mold compound.

14. The package of claim 12 , further comprising a first plurality of bond wires electrically connecting the IC chip to the substrate.

15. The package of claim 14 , further comprising a spacer located between the first main surface of the IC chip and the second main surface the solar cell, wherein the solar cell is mounted on the first main surface of the IC chip by way of the spacer.

16. A method of manufacturing a self-powered circuit package, the method comprising:

mounting an integrated circuit (IC) chip having opposing first and second main surfaces on a first main surface of a substrate;

electrically coupling, using at least one first electrical interconnector, the IC chip to the first main surface of the substrate;

electrically connecting a solar cell having opposing first and second main surfaces to the first main surface of the substrate thereby electrically connecting the solar to the IC chip via the substrate, at least a portion of the first main surface of the solar cell being configured to receive light from an external source, the solar cell being configured to convert energy of the received light into electrical power that is supplied to the IC chip, and wherein the second main surface of the solar cell is in facing arrangement with the first main surface of the IC chip, wherein the solar cell extends over the first main surface of the IC chip, and is mounted and electrically connected to the first main surface of the substrate with solder balls; and

encapsulating, in a mold compound, the IC chip, the at least one first electrical interconnector, at least a portion of the first main surface of the substrate, and at least a portion of the solar cell.

17. The method of claim 16 , further comprising laminating at least the light receiving portion of the first main surface of the solar cell with an encapsulant that is transparent or transmissive to at least a wavelength of the received light.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 030445/0737 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030445/0709 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030445/0581 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2013
From: LAU, TECK BENG; LO, WAI YEW; LOW, BOON YEW; SIONG, CHIN TECK
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029820/0726 →