Methods and systems for selectively forming metal layers on lead frames after die attachment
View Patent ↗Methods and systems are disclosed for selectively forming metal layers on lead frames after die attachment to improve electrical connections for areas of interest on lead frames, such as for example, lead fingers and down-bond areas. By selectively forming metal layers on areas of interest after die attachment, the disclosed embodiments help to eliminate anomalies and associated defects for the lead frames that may be caused by the die attachment process. A variety of techniques can be utilized for selectively forming one or more metal layers, and a variety of metal materials can be used (e.g., nickel, palladium, gold, silver, etc.). Further, cleaning can also be performed with respect to the areas of interest prior to selectively forming the one or more metal layers on areas of interest for the leaf frame.
1. A method for making an integrated circuit package, comprising
attaching a die to a lead frame, the die comprising integrated circuits;
after attaching the die, selectively forming at least one metal plating layer on at least one area of interest for the lead frame, the at least one area of interest being configured for an electrical connection, and the at least one metal plating layer comprising at least one of gold or silver; and
after selectively forming the at least one metal plating layer, forming an electrical connection between the die and the metal plating layer for the at least one area of interest; and
packaging the die, the lead frame, the at least one metal plating layer, and the electrical connection within a lead frame package.
2. The method of claim 1 , wherein the at least one area of interest comprises at least one lead finger for the lead frame.
3. The method of claim 1 , wherein the at least one area of interest comprises at least one down-bond area for the lead frame.
4. The method of claim 1 , wherein the selectively forming step comprises selectively forming a plurality of metal plating layers on at least one area of interest for the lead frame.
5. The method of claim 1 , further comprising utilizing vapor jet deposition to perform the selective forming step.
6. The method of claim 1 , further comprising utilizing atomic layer deposition to perform the selective forming step.
7. The method of claim 1 , further comprising cleaning the at least one area of interest prior to the selectively forming step.
8. The method of claim 7 , further comprising utilizing ion bombardment to perform the cleaning step.
9. The method of claim 1 , further comprising utilizing wire bonding to perform the forming step.
10. The method of claim 1 , wherein the lead frame comprises a copper alloy.
11. The method of claim 1 , wherein the lead frame package comprises at least one of QFP (quad flat pack) packaging, QFN (quad flat no-lead) packaging, SOIC (small outline integrated circuit) packaging, or PQFN (power quad flat no-lead) packaging.