Method and apparatus for reducing the number of speculative accesses to a memory array
View Patent ↗A method includes: receiving a first plurality of consecutive bits from a base operand, wherein a MSB of the first plurality of consecutive bits from the base operand is a LSB of a second plurality of consecutive bits from the base operand; and receiving a first plurality of consecutive bits from an offset operand, wherein a MSB of the first plurality of consecutive bits from the offset operand is a LSB of a second plurality of consecutive bits from the offset operand. The method includes summing the first plurality of consecutive bits from the base operand with the first plurality of consecutive bits from the offset operand to generate a sum value; and allowing access to one of a plurality of memory arrays and disabling access to the remainder of the plurality of memory arrays when a lesser significant bit to a MSB of the sum value equals zero.
1. A method for accessing a memory array, the method comprising:
receiving a first subset of consecutive bits from a base operand, wherein a most significant bit of the first subset of consecutive bits from the base operand is a least significant bit of a second subset of consecutive bits from the base operand;
receiving a first subset of consecutive bits from an offset operand, wherein a most significant bit of the first subset of consecutive bits from the offset operand is a least significant bit of a second subset of consecutive bits from the offset operand,
wherein the first and second subsets of consecutive bits from the base and offset operands are provided to a speculative wordline generation circuit configured to generate a plurality of speculative wordlines each for controlling speculative access of a different memory array of a plurality of memory arrays, and wherein the first subset of consecutive bits from the base operand consists of a number of bits that is no more than a number of bits in the second subset of consecutive bits from the base operand, and the first subset of consecutive bits from the offset operand consists of a number of bits that is no more than a number of bits in the second subset of consecutive bits from the offset operand;
summing the first subset of consecutive bits from the base operand with the first subset of consecutive bits from the offset operand to generate a sum value at the speculative wordline generation circuit; and
allowing speculative access to only one of the plurality of memory arrays and disabling speculative access to the remainder of the plurality of memory arrays when the sum value indicates a carry-kill, wherein the carry-kill is indicated by any lesser significant bit to the most significant bit of the sum value equaling to zero, wherein allowing speculative access to only one of the plurality of memory arrays comprises allowing speculative access to a first memory array of the plurality of memory arrays when the most significant bit of the sum value equals to a first value, and allowing speculative access to a second memory array of the plurality of memory arrays when the most significant bit of the sum value equals to a second value.
2. The method of claim 1 , wherein the plurality of memory arrays comprises a cache within a central processing unit, wherein the second subset of consecutive bits from the base operand comprises a first set of index bits, and the second subset of consecutive bits from the offset operand comprises a second set of index bits, wherein the first and second sets of index bits are used to select a wordline of the cache.
3. The method of claim 1 , wherein the first value equals to one, and the second
value equals to zero.
4. The method of claim 1 , wherein allowing speculative access to the first memory array comprises allowing speculative access to an odd wordline memory bank, and allowing speculative access to the second memory array comprises allowing speculative access to an even wordline memory bank.
5. The method of claim 1 , wherein allowing speculative access to only one of the plurality of memory arrays and disabling speculative access to the remainder of the plurality of memory arrays comprises either: allowing speculative access to the first memory array comprising only odd numbered wordlines and disabling speculative access to the second memory array comprising only even numbered wordlines; or allowing speculative access to the second memory array comprising only the even numbered wordlines and disabling speculative access to the first memory array comprising only the odd numbered wordlines.
6. The method of claim 1 further comprising allowing speculative access to two of the plurality of memory arrays when each lesser significant bit to the most significant bit of the sum value equals to one.
7. The method of claim 6 , wherein the plurality of memory arrays comprises an even wordline array and an odd wordline array that are both speculatively accessed when each lesser significant bit to the most significant bit of the sum value equals to one.
8. The method of claim 1 , wherein the second subset of consecutive bits from the base and offset operands contain four bits, and the first subset of consecutive bits from the base and offset operands both contain a same number of bits, which is no more than four bits.
9. The method of claim 1 , wherein the second subset of consecutive bits from the base and offset operands contain three bits, and the first subset of consecutive bits from the base and offset operands both contain the same amount of bits, which is no more than three bits.
10. The method of claim 1 , wherein summing the first subset of consecutive bits from the base operand with the first subset of consecutive bits from the offset operand to generate the sum value is performed in parallel with summing the second subset of consecutive bits from the base operand with the second subset of consecutive bits from the offset operand to generate at least one memory array index address used to select a wordline from the one of the plurality of memory arrays to which speculative access is allowed.
11. Memory access apparatus comprising:
a plurality of memory arrays comprising a first memory array and a second memory array;
a memory array disable circuit, of a speculative wordline generation circuit, which is coupled to the plurality of memory arrays and configured to:
receive a first subset of consecutive bits from a base operand, wherein a most significant bit of the first subset of consecutive bits from the base operand is a least significant bit of a second subset of consecutive bits from the base operand;
receive a first subset of consecutive bits from an offset operand, wherein a most significant bit of the first subset of consecutive bits from the offset operand is a least significant bit of a second subset of consecutive bits from the offset operand, wherein the first and second subsets of consecutive bits from the base and offset operands are provided to the speculative wordline generation circuit configured to generate a plurality of speculative wordlines each for controlling speculative access of a different memory array of a plurality of memory arrays, and wherein the first subset of consecutive bits from the base operand consists of a number of bits that is no more than a number of bits in the second subset of consecutive bits from the base operand, and the first subset of consecutive bits from the offset operand consists of a number of bits that is no more than a number of bits in the second subset of consecutive bits from the offset operand;
sum the first subset of consecutive bits from the base operand with the first subset of consecutive bits from the offset operand to generate a sum value at the speculative wordline generation circuit; and
allow speculative access to only one of the plurality of memory arrays and disable speculative access to the remainder of the plurality of memory arrays when the sum value indicates a carry-kill, wherein the carry-kill is indicated by any lesser significant bit to the most significant bit of the sum value equaling to zero, wherein allowing speculative access to only one of the plurality of memory arrays comprises allowing speculative access to a first memory array of the plurality of memory arrays when the most significant bit of the sum value equals to a first value, and allowing speculative access to a second memory array of the plurality of memory arrays when the most significant bit of the sum value equals to a second value.
12. The memory array apparatus of claim 11 ,
wherein the memory array disable circuit is configured to either: allow speculative access to the first memory array when the most significant bit of the sum value equals to one or allow speculative access to the second memory array when the most significant bit of the sum value equals to zero.
13. The memory array apparatus of claim 12 , wherein the first memory array is an odd wordline memory bank, and the second memory array is an even wordline memory bank.
14. The memory array apparatus of claim 11 , wherein the first memory array comprises an even array having only even wordlines and the second memory array comprises an odd array having only odd wordlines, the memory array apparatus further comprising:
a speculative even wordline generator coupled between the memory array disable circuit and the even array and configured to generate at least one even wordline signal for speculatively accessing an even wordline from the even array; and
a speculative odd wordline generator coupled between the memory array disable circuit and the odd array and configured to generate at least one odd wordline signal for speculatively accessing an odd wordline from the odd array;
wherein the memory array disable circuit is configured, when the lesser significant bit to the most significant bit of the sum value equals to zero, to either: allow speculative access to the even array and disable the at least one odd wordline signal to disable speculative access to the odd array; or allow speculative access to the odd array and disable the at least one even wordline signal to disable speculative access to the even array.
15. The memory array apparatus of claim 14 , wherein the memory array disable circuit is configured to allow speculative access to both the even and the odd array when each lesser significant bit to the most significant bit of the sum value equals to one.
16. A method for accessing a memory array, the method comprising:
summing a first set of bits with a second set of bits to generate a sum value at a speculative wordline generation circuit, wherein the first set of bits comprises at least two consecutive bits from a base operand, wherein a most significant bit of the first set of bits is a least significant bit of a base index address from the base operand, wherein the second set of bits comprises at least two consecutive bits from an offset operand, wherein a most significant bit of the second set of bits is a least significant bit of an offset index address from the offset operand, wherein the first and second sets of bits from the base and offset operands are provided to the speculative wordline generation circuit which is configured to generate a plurality of speculative wordlines each for controlling speculative access of a different memory array of a plurality of memory arrays, and wherein the first set of bits from the base operand consists of a number of bits that is no more than a number of bits in the second set of bits from the base operand, and the first set of bits from the offset operand consists of a number of bits that is no more than a number of bits in the second set of bits from the offset operand; and
disabling speculative access to one and allowing speculative access to one of two memory arrays, comprising an odd wordline memory array and an even wordline memory array, when the sum value indicates a carry-kill, wherein the carry-kill is indicated by any lesser significant bit to the most significant bit of the sum value equals to zero, wherein disabling access to one and allowing speculative access to one of the two memory arrays comprises disabling speculative access to the odd wordline memory array and allowing speculative access to the even wordline memory array when the most significant bit of the sum value equals to a first value, and disabling speculative access to the even wordline memory array and allowing speculative access to the odd wordline memory array when the most significant bit of the sum value equals to a second value.
17. The method of claim 16 , wherein disabling speculative access to one and allowing speculative access to one of the two memory arrays comprises:
disabling speculative access to the odd wordline memory array and allowing speculative access to the even wordline memory array when the most significant bit of the sum value equals to zero;
disabling speculative access to the even wordline memory array and allowing speculative access to the odd wordline memory array when the most significant bit of the sum value equals to one.
18. The method of claim 16 further comprising allowing speculative access to both the odd and the even wordline memory arrays when each lesser significant bit to the most significant bit of the sum value equals to one.
19. The method of claim 16 , wherein the base index address and the offset index address both contain a same number of bits, which is equal to three bits or four bits, and the first and second sets of bits from the base and offset operands both contain a same number of bits, which is no more than four bits.