Resolution programmable dynamic IR-drop sensor with peak IR-drop tracking abilities
View Patent ↗A data processing system on an integrated circuit includes a core that performs switching operations responsive to a system clock that draws current from the power supply network. An IR-drop detector includes a resistor ladder having outputs representative of an IR-drop caused by the core during the switching operations. The system further includes a plurality of amplifiers coupled to the outputs indicative of the IR-drop, a plurality of flip-flops coupled to the amplifiers, and a variable clock generator. The variable clock generator outputs a sampling clock comprising a group consisting of a variable phase or a variable frequency to the plurality of flip-flops. The flip-flops are triggered by the sampling clock so that the IR-drop at a time during a clock cycle of the system clock can be detected, and the peak IR-drop value for can be tracked.
1. A data processing system on an integrated circuit, comprising:
a core, coupled to a power supply network that performs switching operations responsive to a system clock that draws current from the power supply network; and
an IR-drop detector, comprising:
a resistor ladder, coupled to the power supply network, having a plurality of outputs representative of an IR-drop caused by the core during the switching operations;
a plurality of amplifiers, coupled to the plurality of outputs;
a plurality of flip-flops coupled to the plurality of outputs of the plurality of amplifiers; and
a variable clock generator that outputs a sampling clock comprising a first feature of a group consisting of a variable phase or a variable frequency to the plurality of flip-flops, wherein the plurality of flip-flops are triggered by the sampling clock so that the IR-drop at a sampling time can be detected.
2. The data processing system of claim 1 , wherein the IR-drop detector further comprises:
a first voltage calibration circuit coupled between the first terminal of the resistor ladder and the power supply network.
3. The data processing system of claim 2 , wherein:
the plurality of amplifiers is characterized as having a threshold voltage and a configurable resolution; and
the first voltage calibration circuit is variable to optimize a location of a voltage range of the resistor ladder relative to the threshold voltage.
4. The data processing system of claim 3 , further comprising;
a second calibration circuit coupled between the second terminal of the resistor ladder and a ground terminal.
5. The data processing system of claim 4 , wherein the first voltage calibration circuit comprises a plurality of loads selectively coupled in parallel.
6. The data processing system of claim 5 , wherein the second calibration circuit comprises a plurality of loads selectively coupled in series.
7. The data processing system of claim 1 , wherein the first feature is the variable frequency and the variable frequency is greater than a frequency of the system clock.
8. The data processing system of claim 5 , further comprising a second feature, wherein the second feature comprises the variable phase.
9. The data system of claim 1 , wherein the plurality of amplifiers comprises a first amplifier, wherein the first amplifier comprises:
an N channel transistor having a gate coupled to a first output of the plurality of outputs, a source coupled to a ground terminal, and a drain; and
a P channel transistor having a gate coupled to the first output of the plurality of outputs, a source connected to the power supply network, and a drain coupled to the drain of the N channel transistor.
10. The data system of claim 1 , wherein the variable clock generator is responsive to the system clock.
11. A data processing system on an integrated circuit, comprising:
a core, coupled to a first power supply network, that performs switching operations responsive to a system clock that cause an IR-drop from the first power supply network; and
an IR-drop detector, comprising:
a first voltage calibration circuit having a first terminal coupled to the first power supply network and a second terminal; and
a resistor ladder having a first terminal coupled to the second terminal of the first voltage calibration circuit and a second terminal, wherein the resistor ladder has a plurality of outputs between the first terminal and the second terminal of the resistor ladder;
a first plurality of voltage sensors coupled to the outputs of the resistor ladder;
wherein: the outputs of the resistor ladder are representative of the IR-drop;
each voltage sensor of the plurality of voltage sensors has a first threshold voltage; and
the first voltage calibration circuit is variable to optimize a location of a voltage range of the resistor ladder relative to the first threshold voltage.
12. The data processing system of claim 11 , wherein:
each of the plurality of voltage sensors has a first threshold voltage; and
when the IR-drop is increased, fewer inputs of the plurality of sensors exceeds the first threshold voltage.
13. The data processing system of claim 11 , further comprising a variable clock generator providing a sampling clock coupled to the plurality of voltage sensors.
14. The data processing system of claim 13 , wherein the variable clock generator can vary the frequency and phase of the sampling clock.
15. The data processing system of claim 14 , wherein the plurality of voltage sensors can indicate the IR-drop at a plurality of locations within a period of the system clock.
16. A method for operating a data processing system having a core coupled to a first power supply network, comprising:
operating the core to cause an IR-drop at the first power supply network responsive to a first clock having a phase and a frequency;
using a resistor ladder to generate a plurality of outputs representative of the IR-drop;
receiving the plurality of outputs with a plurality of flip-flops clocked with a second clock having a phase and a sampling frequency;
providing an output indicative of the IR-drop from the plurality of flip-flops responsive to the second clock.
17. The method of claim 16 , wherein the step of providing the output indicative of the IR-drop is further characterized by the second clock having a different phase from the first clock.
18. The method of claim 16 , wherein the providing the output indicative of the IR-drop is further characterized by the second clock having a different frequency from the first clock.
19. The method of claim 18 , wherein the providing the output indicative of the IR-drop provides the output indicative of the IR-drop at the frequency of the second clock.
20. The method of claim 16 , wherein the first clock has a time period between first edges of the first clock, wherein the step of providing the output indicative of the IR-drop is further characterized by the output indicative of the IR-drop being provided for a selectable time within the time period between the first edges.