IP Library Granted Patent US 8,797,078
Granted Patent B2
US 8,797,078 · App. 13/811,921 · Granted Aug 5, 2014

Latch circuit, flip-flop circuit and frequency divider

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Quick Facts
Patent No.
US 8,797,078
App. No.
13/811,921
Granted
Aug 5, 2014
Kind
B2
Abstract

The invention pertains to a latch circuit comprising a sensing arrangement with one or more sensing transistors adapted to sense an input signal and to provide a first signal based on the sensed input signal, and a sensing arrangement switch device connected or connectable to a first current source, the sensing arrangement switch device being adapted to switch on or off a current to the one or more sensing transistors based on a first clock signal. The latch circuit further comprises a storage arrangement with one or more storage transistors adapted to store the first signal and to provide a second signal based on the first signal, and a storage arrangement switching device connected or connectable to the first current source or a second current source, the storage arrangement switching device being adapted to switch on or off a current to the storage transistors based on a second clock signal, as well as a tuning arrangement connected or connectable to a temperature sensor, the tuning arrangement being adapted to bias a current of the sensing arrangement and/or the storage arrangement based on a temperature signal provided by the temperature sensor. The invention also pertains to a flip-flop circuit with two or more latch circuits and a frequency divider comprising at least one latch circuit as described.

Claims (28)

1. A latch circuit comprising:

a sensing arrangement comprising:

one or more sensing transistors adapted to sense an input signal and to provide a first signal based on the sensed input signal, and

a sensing arrangement switch device connected or connectable to a first current source, the sensing arrangement switch device being adapted to switch on or off a current to the one or more sensing transistors based on a first clock signal;

wherein the latch circuit further comprises a storage arrangement comprising:

one or more storage transistors adapted to store the first signal and to provide a second signal based on the first signal, and

a storage arrangement switching device connected or connectable to the first current source or a second current source, the storage arrangement switching device being adapted to switch on or off a current to the storage transistors based on a second clock signal;

wherein the latch circuit further comprises:

a tuning arrangement connected or connectable to a temperature sensor), the tuning arrangement being adapted to bias a current of the sensing arrangement and/or the storage arrangement based on a temperature signal provided by the temperature sensor.

2. The latch circuit of claim 1 , wherein the tuning arrangement is connected or connectable to the first, the second or a third current source.

3. The latch circuit of claim 2 , wherein the tuning arrangement provides a tuning current for biasing the current of the sensing arrangement and/or the storage arrangement.

4. The latch circuit according to claim 3 , wherein the tuning arrangement is connected to a connection point between a sensing section of the sensing arrangement and the sensing arrangement switch device and/or to a connection point between a storage section of the storage arrangement and the storage arrangement switch device to bias the current of the sensing arrangement and/or the storage arrangement.

5. The latch circuit according to claim 3 , wherein the tuning arrangement is adapted to bias the current level of the sensing arrangement and/or the storage arrangement such that the current level in the sensing arrangement when the sensing arrangement switch device is switched off is higher than the current level in the storage arrangement when then storage arrangement switch device is switched off.

6. A flip-flop circuit comprising two or more latch circuits, at least one of the latch circuits being a latch circuit according to claim 3 .

7. The latch circuit of claim 2 , wherein the tuning arrangement provides a tuning voltage for controlling a tuning current, the tuning voltage depending linearly on the temperature signal.

8. The latch circuit according to claim 2 , wherein the tuning arrangement is connected to a connection point between a sensing section of the sensing arrangement and the sensing arrangement switch device and/or to a connection point between a storage section of the storage arrangement and the storage arrangement switch device to bias the current of the sensing arrangement and/or the storage arrangement.

9. The latch circuit according to claim 2 , wherein the tuning arrangement is adapted to bias the current level of the sensing arrangement and/or the storage arrangement such that the current level in the sensing arrangement when the sensing arrangement switch device is switched off is higher than the current level in the storage arrangement when then storage arrangement switch device is switched off.

10. The latch circuit according to claim 2 , wherein the tuning arrangement is adapted to provide a current to the storage arrangement in a direction opposite to a direction of the current switched on by the storage arrangement switching device.

11. A flip-flop circuit comprising two or more latch circuits, at least one of the latch circuits being a latch circuit according to claim 2 .

12. The latch circuit according to claim 1 , wherein the tuning arrangement is connected to a connection point between a sensing section of the sensing arrangement and the sensing arrangement switch device and/or to a connection point between a storage section of the storage arrangement and the storage arrangement switch device to bias the current of the sensing arrangement and/or the storage arrangement.

13. The latch circuit according to claim 1 , wherein the tuning arrangement is adapted to bias the current level of the sensing arrangement and/or the storage arrangement such that the current level in the sensing arrangement when the sensing arrangement switch device is switched off is higher than the current level in the storage arrangement when then storage arrangement switch device is switched off.

14. The latch circuit according to claim 12 , wherein the tuning arrangement is adapted to bias the current level of the sensing arrangement and/or the storage arrangement such that the current level in the sensing arrangement when the sensing arrangement switch device is switched off is higher than the current level in the storage arrangement when then storage arrangement switch device is switched off.

15. The latch circuit according to claim 1 , wherein the tuning arrangement is adapted to provide a current to the storage arrangement in a direction opposite to a direction of the current switched on by the storage arrangement switching device.

16. The latch circuit of claim 1 , wherein the tuning arrangement comprises a temperature sensor.

17. A flip-flop circuit comprising two or more latch circuits, at least one of the latch circuits being a latch circuit according to claim 1 .

18. A frequency divider comprising at least one latch circuit according to claim 1 .

19. The frequency divider according to claim 18 , comprising a first latch circuit and a second latch circuit, the first latch circuit providing a first output signal as an input signal for the second latch circuit, the first latch circuit and/or the second latch circuit being a latch circuit according to claim 1 .

20. The frequency divider according to claim 18 , the frequency divider comprising a control device adapted to receive temperature signals of one or more temperature sensors and to control one or more tuning arrangements of latch circuits based on the temperature signals.

Assignments (27)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2013
From: TROTTA, SAVERIO
To: FREESCALE SEMICONDUCTOR INC
Reel/Frame 029683/0863 →