Die edge sealing structures and related fabrication methods
View Patent ↗Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer.
1. A die structure comprising:
a diced portion of a semiconductor substrate including a first layer of semiconductor material, a buried layer of dielectric material, and a handle layer of semiconductor material, the buried layer overlying the handle layer and the first layer overlying the buried layer, the diced portion including a device region of the first layer, the device region having one or more semiconductor devices fabricated thereon;
a sealing structure within the first layer of the semiconductor substrate and the buried layer of dielectric material, the sealing structure contacting the handle layer and circumscribing the device region; and
a crackstop structure circumscribing the device region, the crackstop structure overlying the sealing structure, wherein the crackstop structure and the sealing structure cooperate to electrically connect the handle layer to the first layer to provide a voltage of the handle layer as a reference voltage for the device region.
2. The die structure of claim 1 , further comprising a contact region within the first layer of the device region proximate the sealing structure, the contact region circumscribing the one or more semiconductor devices, wherein the contact region is electrically connected to the sealing structure.
3. The die structure of claim 2 , wherein the sealing structure circumscribes the contact region.
4. The die structure of claim 2 , wherein the crackstop structure overlies the contact region and the sealing structure to electrically connect the contact region to the sealing structure.
5. The die structure of claim 4 , wherein the crackstop structure comprises:
a first vertical conductive structure overlying the contact region;
a second vertical conductive structure overlying the sealing structure; and
one or more conductive lateral interconnections between the first vertical conductive structure and the second vertical conductive structure.
6. The die structure of claim 1 , wherein:
the crackstop structure electrically connects the first layer to the sealing structure; and
the sealing structure is electrically connected to the handle layer.
7. The die structure of claim 1 , wherein the sealing structure comprises a conductive material within an outermost deep trench isolation region in the diced portion of the semiconductor substrate.
8. The die structure of claim 1 , wherein the crackstop structure comprises portions of via layers and metallization layers patterned to provide a vertical conductive structure.
9. The die structure of claim 8 , wherein the crackstop structure is configured to provide protection from lateral propagation of cutting defects in one or more of the via layers or the metallization layers to the one or more of the via layers or the metallization layers overlying the device region.
10. The die structure of claim 1 , wherein the crackstop structure is formed about a perimeter of the device region to surround the one or more semiconductor devices.
11. The die structure of claim 1 , wherein the sealing structure is at or near a perimeter of the device region.
12. A die structure comprising:
a diced portion of a semiconductor substrate including a first layer of semiconductor material, a buried layer of dielectric material, and a handle layer of semiconductor material, the buried layer overlying the handle layer and the first layer overlying the buried layer, the diced portion including a device region of the first layer, the device region having one or more semiconductor devices fabricated thereon;
a sealing structure within the first layer of the semiconductor substrate and the buried layer of dielectric material, the sealing structure circumscribing the device region and contacting the handle layer; and
a contact region within the first layer of the device region, wherein:
the contact region is electrically connected to the sealing structure;
the contact region and the first layer have a first conductivity type; and
the sealing structure and the handle layer have a second conductivity type.
13. A device comprising:
a semiconductor substrate including a handle layer of semiconductor material, a buried layer of dielectric material on the handle layer, and a first layer of semiconductor material on the buried layer;
a sealing structure within the semiconductor substrate, the sealing structure circumscribing a device region of the semiconductor substrate between the device region and an edge region of the semiconductor substrate; and
a crackstop structure overlying the sealing structure, the crackstop structure providing an electrical interconnection between the first layer and the sealing structure, wherein the sealing structure electrically connects the crackstop structure to the handle layer to provide a voltage of the handle layer as a reference voltage for the device region.
14. The device of claim 13 , wherein the sealing structure comprises a conductive material within the first layer and the buried layer that contacts the handle layer.
15. The device of claim 14 , further comprising a doped contact region within the device region proximate the sealing structure, wherein the crackstop structure overlies the doped contact region and the conductive material and electrically connects the conductive material to the device region of the first layer.
16. The device of claim 15 , wherein:
the device region includes one or more semiconductor devices fabricated thereon; and
the contact region circumscribes the one or more semiconductor devices.
17. The device of claim 13 , wherein the crackstop structure comprises portions of via layers and metallization layers patterned to provide a vertical conductive structure.
18. The device of claim 13 , wherein the crackstop structure is formed about a perimeter of the device region to surround semiconductor devices fabricated on the device region.
19. A device comprising:
a semiconductor substrate including a handle layer of semiconductor material, a buried layer of dielectric material on the handle layer, and a first layer of semiconductor material on the buried layer;
a sealing structure within the semiconductor substrate between a device region of the semiconductor substrate and an edge region of the semiconductor substrate;
a crackstop structure overlying the sealing structure, wherein the sealing structure electrically connects the crackstop structure to the handle layer; and
an outer crackstop structure on the edge region of the semiconductor substrate, the outer crackstop structure circumscribing the crackstop structure.