Prioritized design for manufacturing virtualization with design rule checking filtering
View Patent ↗An approach is provided to generate a number of virtualized circuit designs by applying design-for-manufacturing (DFM) processes to a circuit design. The virtualized circuit designs are checked using design rule checks (DRCs), with the checking resulting in a design rule error quantity that corresponds to each of the virtualized circuit designs. One of the virtualized circuit designs is selected for use in manufacturing the circuit design with the selection based each of the design's design rule error quantities.
1. A method performed by an information handling system that runs one or more software tools, the method comprising:
generating a plurality of virtualized circuit designs by applying a plurality of design-for-manufacturing (DFM) processes to a circuit design, the generating performed by at least one processor that executes one of the software tools running on the information handling system, and wherein the virtualized circuit designs and the circuit design are stored in a memory included in the information handling system;
checking, using one of the software tools running on the information handling system, the plurality of virtualized circuit designs with a plurality of design rule checks (DRGs), the checking resulting in a design rule error quantity corresponding to each of the virtualized circuit designs, the checking performed by at least one processor that executes one of the software tools running on the information handling system, and wherein the design rule error quantity is stored in the memory included in the information handling system; and
based on the corresponding design rule error quantities, selecting one of the virtualized circuit designs to use in manufacturing the circuit design.
2. The method of claim 1 wherein the checking further results in one or more design rule check violations corresponding to each of the virtualized circuit designs with design rule error quantities greater than zero, wherein the method further comprising:
checking the circuit design with the plurality of DRCs, the checking resulting in a baseline set of violated DRC rules;
analyzing the baseline set of violated DRC rules, wherein the analysis results in a set of waived DRC rules to ignore;
removing the design rule check violations that match one of the waived DRC rules to ignore; and
reducing the design rule error quantities based upon the removal of the design rule check violations.
3. The method of claim 2 further comprising:
after the reduction of design rule error quantities:
comparing the design rule error quantity corresponding to each of the virtualized circuit designs with a threshold; and
generating a set of one or more selectable virtualized circuit designs from the one or more virtualized circuit design by removing any of the virtualized circuit designs with design rule error quantities that exceed the threshold, wherein the selected virtualized circuit designs is selected from the set of selectable virtualized circuit designs.
4. The method of claim 3 wherein the threshold is set to zero so that any of the virtualized circuit designs that introduce one or more new DRC errors are removed from the set of selectable virtualized circuit designs.
5. The method of claim 1 wherein the plurality of DFM processes are ordered based upon a priority.
6. The method of claim 1 wherein the selection of the virtualized circuit design to use in manufacturing the circuit design is further based on the DFM process used to generate the corresponding virtual circuit design.
7. The method of claim 6 wherein the selection is further based on a priority assigned to the DFM process used to generate the corresponding virtual circuit design.
8. An information handling system comprising:
one or more processors;
a memory coupled to at least one of the processors;
a set of instructions stored in the memory and executed by at least one of the processors to increase password strength, wherein the set of instructions perform actions of:
generating a plurality of virtualized circuit designs by applying a plurality of design-for-manufacturing (DFM) processes to a circuit design;
checking the plurality of virtualized circuit designs with a plurality of design rule checks (DRGs), the checking resulting in a design rule error quantity corresponding to each of the virtualized circuit designs; and
based on the corresponding design rule error quantities, receiving a selection of one of the virtualized circuit designs to use in manufacturing the circuit design.
9. The information handling system of claim 8 wherein the checking further results in one or more design rule check violations corresponding to each of the virtualized circuit designs with design rule error quantities greater than zero, and wherein the actions further comprise:
checking the circuit design with the plurality of DRCs, the checking resulting in a baseline set of violated DRC rules;
analyzing the baseline set of violated DRC rules, wherein the analysis results in a set of waived DRC rules to ignore;
removing the design rule check violations that match one of the waived DRC rules to ignore; and
reducing the design rule error quantities based upon the removal of the design rule check violations.
10. The information handling system of claim 9 wherein the actions further comprise:
after the reduction of design rule error quantities:
comparing the design rule error quantity corresponding to each of the virtualized circuit designs with a threshold; and
generating a set of one or more selectable virtualized circuit designs from the one or more virtualized circuit design by removing any of the virtualized circuit designs with design rule error quantities that exceed the threshold, wherein the selected virtualized circuit designs is selected from the set of selectable virtualized circuit designs.
11. The information handling system of claim 10 wherein the threshold is set to zero so that any of the virtualized circuit designs that introduce one or more new DRC errors are removed from the set of selectable virtualized circuit designs.
12. The information handling system of claim 8 wherein the plurality of DFM processes are ordered based upon a priority.
13. The information handling system of claim 8 wherein the selection of the virtualized circuit design to use in manufacturing the circuit design is further based on the DFM process used to generate the corresponding virtual circuit design.
14. The information handling system of claim 13 wherein the selection is further based on a priority assigned to the DFM process used to generate the corresponding virtual circuit design.
15. A computer program product stored in a non-transitory computer readable storage medium, comprising computer program code that, when executed by an information handling system, causes the information handling system to perform actions comprising:
generating a plurality of virtualized circuit designs by applying a plurality of design-for-manufacturing (DFM) processes to a circuit design;
checking the plurality of virtualized circuit designs with a plurality of design rule checks (DRGs), the checking resulting in a design rule error quantity corresponding to each of the virtualized circuit designs; and
based on the corresponding design rule error quantities, selecting one of the virtualized circuit designs to use in manufacturing the circuit design.
16. The computer program product of claim 15 wherein the checking further results in one or more design rule check violations corresponding to each of the virtualized circuit designs with design rule error quantities greater than zero, and wherein the actions further comprise:
checking the circuit design with the plurality of DRCs, the checking resulting in a baseline set of violated DRC rules;
analyzing the baseline set of violated DRC rules, wherein the analysis results in a set of waived DRC rules to ignore;
removing the design rule check violations that match one of the waived DRC rules to ignore; and
reducing the design rule error quantities based upon the removal of the design rule check violations.
17. The computer program product of claim 16 wherein the actions further comprise:
after the reduction of design rule error quantities:
comparing the design rule error quantity corresponding to each of the virtualized circuit designs with a threshold; and
generating a set of one or more selectable virtualized circuit designs from the one or more virtualized circuit design by removing any of the virtualized circuit designs with design rule error quantities that exceed the threshold, wherein the selected virtualized circuit designs is selected from the set of selectable virtualized circuit designs.
18. The computer program product of claim 15 wherein the plurality of DFM processes are ordered based upon a priority.
19. The computer program product of claim 15 wherein the selection of the virtualized circuit design to use in manufacturing the circuit design is further based on the DFM process used to generate the corresponding virtual circuit design.
20. The computer program product of claim 19 wherein the selection is further based on a priority assigned to the DFM process used to generate the corresponding virtual circuit design.