Variable delay and setup time flip-flop
View Patent ↗An apparatus is provided. The apparatus includes a flip-flop including an input configured to receive a setup time and delay control (SDC) signal, and an output buffer including first and second conductive paths. The second conductive path is non-conductive when the SDC signal has a first value at the input and is conductive when the SDC signal has a second value at the input. The apparatus includes a propagation delay sensor configured to estimate a propagation delay of the flip-flop, and, when the estimated propagation delay exceeds a threshold, supply the SDC signal having the second value to the input of the flip-flop.
1. An apparatus, comprising:
a flip-flop including:
a first input configured to receive a first setup time and delay control (SDC) signal,
a second input configured to receive a second SDC signal, and
an output buffer including first, second, and third conductive paths, the second conductive path being non-conductive when the first SDC signal has a first value at the first input and being conductive when the first SDC signal has a second value at the first input and the third conductive path being conductive when the second SDC signal has a third value at the second input; and
a propagation delay sensor configured to:
estimate a propagation delay of the flip-flop,
compare the propagation delay to a first threshold and a second threshold, and
when the estimated propagation delay exceeds the first threshold, supply the first SDC signal having the second value to the first input of the flip-flop and when the estimated propagation delay exceeds the second threshold, supply the second SDC signal having the third value to the second input of the flip-flop.
2. The apparatus of claim 1 , wherein the propagation delay sensor is a process, voltage, temperature sensor.
3. The apparatus of claim 1 , wherein the flip-flop includes a clock delay stage controlled by the first SDC signal and the second SDC signal.
4. The apparatus of claim 3 , wherein, when the first SDC signal has the second value at the first input, the clock delay stage operates to delay a clock signal received by the flip-flop.
5. The apparatus of claim 4 , wherein, when the first SDC signal has the first value at the first input, the clock delay stage is not operative.
6. The apparatus of claim 1 , wherein the propagation delay sensor is configured to supply the first SDC signal having the first value to the first input of the flip-flop when the estimated propagation delay does not exceed the first threshold.
7. The apparatus of claim 1 , wherein the first threshold is (Tperiod/2+Thold)*n, where Tperiod is a system clock period of the apparatus and Thold is the hold time of a flip-flop of the propagation delay sensor, and n is a value equal to or greater than 1.
8. The apparatus of claim 1 , wherein the second threshold is (Tperiod/2+Thold)+((Tperiod−Tsetup)−(Tperiod/2+Thold))/2, where Tperiod is a system clock period of the apparatus, Thold is the hold time of the flip-flop of the propagation delay sensor, and Tsetup is a setup time of the flip-flop of the propagation delay sensor.
9. The apparatus of claim 1 , including a second flip-flop having an input configured to receive the first SDC signal, the first flip-flop belonging to a first clock domain and the second flip-flop belonging to the first clock domain.