Voltage switching circuitry, integrated device and integrated circuit, and method of voltage switching
View Patent ↗A voltage switching circuitry comprises a switching arrangement with a given number N of switches in series between a first terminal receiving a first voltage and a second terminal receiving a second voltage. The first voltage level is higher than the second voltage level, and N is at least equal to 2. A voltage-by-N divider, having N−1 output taps, is arranged to divide the first voltage by N to a scaled down version of the first voltage having a voltage level below voltage max ratings of the switches. The N−1 output taps of the divider are arranged to respectively output N−1 third voltages having respective levels staged below the first voltage level. N−1 max voltage generators generate N−1 fourth voltages, respectively equal to the maximum of the second voltage and of each of the N−1 third voltages. A switch control unit generates N control signals using the N−1 fourth voltages. These N control signals have respective voltage levels staged between the first voltage level and the second voltage level. In addition, each of the N control signals controls one of the switches of the switching arrangement, respectively.
1. A voltage switching circuitry comprising:
at least one switching arrangement with a given number, N, of switches in series between a first terminal for receiving a first voltage at a first voltage level and a second terminal for receiving a second voltage at a second voltage level, the first voltage level being higher than the second voltage level, and N being at least equal to 2;
a voltage-by-N divider having N−1 output taps, arranged to divide the first voltage by N to a scaled down version of the first voltage having a voltage level below voltage max ratings of the switches, wherein the N−1 output taps of the divider are arranged to respectively output N−1 third voltages having respective levels staged below the first voltage level;
N−1 max voltage generators for generating N−1 fourth voltages, respectively equal to the maximum of the second supply voltage and of each of the N−1 third voltages; and
a switch control unit for generating N control signals using the N−1 fourth voltages, said N control signals having respective voltage levels staged between the first voltage level and the second voltage level, and each of said N control signals controlling one of the switches of the switching arrangement, respectively.
2. The voltage switching circuitry of claim 1 , wherein the switches are PMOS transistors.
3. The voltage switching circuitry of claim 1 , wherein the voltage-by-N divider comprises N diode-connected MOS transistors in series between a terminal at the first voltage and a terminal at the potential of the ground.
4. The voltage switching circuitry of claim 2 , wherein the voltage-by-N divider comprises N diode-connected MOS transistors in series between a terminal at the first voltage and a terminal at the potential of the ground.
5. An integrated circuit device comprising:
a first terminal for receiving a first voltage at a first voltage level;
a second terminal for receiving a second voltage at a second voltage level, the first voltage level being higher than the second voltage level; and
a voltage switching circuitry of claim 1 .
6. The integrated device of claim 5 , comprising a second switching arrangement with N switches in series between the first terminal and a third terminal for receiving a third voltage at a third voltage level, where the first voltage level is higher than the third voltage level, wherein N second control signals controlling the switches of the second switching arrangement are further generated by the switch control unit using the N−1 fourth voltages, said N second control signals having respective voltage levels staged between the first voltage level and the third voltage level.
7. The integrated device of claim 6 , wherein the third terminal is a ground terminal, and wherein the switches of the second switching arrangements are NMOS transistors.
8. The integrated device of claim 6 , wherein the voltage-by-N divider comprises N diode-connected MOS transistors in series between a terminal at the first voltage and a terminal at the ground potential.
9. The integrated device of claim 5 , wherein the switches of the first switching arrangement are PMOS transistors.
10. The integrated device of claim 9 , wherein the third terminal is a ground terminal, and wherein the switches of the second switching arrangements are NMOS transistors.
11. The integrated device of claim 9 , wherein the voltage-by-N divider comprises N diode-connected MOS transistors in series between a terminal at the first voltage and a terminal at the ground potential.
12. The integrated device of claim 5 , wherein the voltage-by-N divider comprises N diode-connected MOS transistors in series between a terminal at the first voltage and a terminal at the ground potential.
13. An integrated circuit comprising:
a Non Volatile Memory block having an input terminal on which a first voltage at a first voltage level or a second voltage at a second voltage level may be applied, where the first voltage level is higher than the second voltage level;
a voltage source having an output terminal delivering the second voltage;
a pad which may receive the first voltage from the exterior of the circuit and which is directly connected to the input terminal of the Non Volatile Memory block; and
a voltage switching circuitry comprising:
a first switching arrangement with a given number N of switches in series between the input terminal of the Non Volatile Memory block and the pad, where N is at least equal to 2;
a second switching arrangement with N switches in series between the input terminal of the Non Volatile Memory block and a ground terminal;
a voltage-by-N divider, having N−1 output taps, arranged to divide the first voltage by N to a scaled down version of the first voltage having a voltage level below voltage max ratings of the switches, wherein the N−1 output taps of the divider are arranged to respectively output N−1 third voltages having respective levels staged below the first voltage level;
N−1 max voltage generators for generating N−1 fourth voltages, respectively equal to the maximum of the second voltage and of each of the N−1 third voltages;
a switch control unit for generating N first control signals using the N−1 fourth voltages, said N first control signals having respective voltage levels staged between the first voltage and the second voltage, each of said N first control signals controlling one of the switches of the first switching arrangement, respectively; and,
N second control signals using the N−1 fourth voltages, said N second control signals having respective voltage levels staged between the first voltage and the third voltage, each of said N second control signals controlling one of the switches of the second switching arrangement, respectively.
14. The integrated circuit of claim 13 , wherein the switches of the first switching arrangement are PMOS transistors.
15. The integrated circuit of claim 14 , wherein the switches of the second switching arrangements are NMOS transistors.
16. The integrated device of claim 14 , wherein the voltage-by-N divider comprises N diode-connected MOS transistors in series between the pad and the ground terminal.
17. The integrated circuit of claim 13 , wherein the switches of the second switching arrangements are NMOS transistors.
18. The integrated device of claim 13 , wherein the voltage-by-N divider comprises N diode-connected MOS transistors in series between the pad and the ground terminal.
19. A method of managing voltage switching between a first terminal receiving a first voltage at a first voltage level and a second terminal receiving a second voltage at a second voltage level, where the first voltage level is higher than the second voltage level, comprising:
dividing the first voltage by a given number N, where N is at least equal to 2, to a scaled down version of the first voltage having a voltage level below voltage max ratings of available switches, and generating N−1 third voltages having respective levels staged below the first voltage level;
generating N−1 fourth voltages, respectively equal to the maximum of the second voltage and of each of the N−1 third voltages, respectively;
generating N first control signals using the N−1 fourth voltages, said N first control signals having respective voltage levels staged between the first voltage level and the second voltage level, and; and,
controlling at least a first switching arrangement with N switches in series between the first terminal and the second terminal, each one of the switches of said first switching arrangement being controlled by one of the N first control signals, respectively.
20. The method of claim 19 , further comprising:
generating N second control signals using the N−1 fourth voltages, said N second control signals having respective voltage levels staged between the first voltage level and a third voltage level, where the first voltage level is higher than the third voltage level; and,
controlling a second switching arrangement with N switches in series between the first terminal and a third terminal receiving the third voltage, each one of the switches of said second switching arrangement being controlled by one of the N second control signals, respectively.