Granted Patent B2

US 8,877,568 · App. 13/781,727 · Granted Nov 4, 2014

Abstract

Claims (50)

1. A method of making a logic transistor in a logic region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising:

forming a gate dielectric layer on the substrate;

forming a first conductive layer on the gate dielectric;

patterning the first conductive layer over the NVM region and removing the first conductive layer over the logic region;

forming a dielectric layer over the NVM region including the first conductive layer and over the logic region;

forming a protective layer over the dielectric layer;

removing the dielectric layer and the protective layer from the logic region to leave a remaining portion of the dielectric layer and a remaining portion of the protective layer over the NVM region;

forming a high-k dielectric layer over the logic region and the remaining portion of the protective layer;

forming a first metal layer over the high-k dielectric layer;

removing the first metal layer, the high-k dielectric, and the remaining portion of the protective layer over the NVM region to leave a remaining portion of the first metal layer and a remaining portion of the high-k dielectric layer over the logic region;

forming a second conductive layer over the remaining portion of the dielectric layer and over the first metal layer; and

forming the NVM cell and the logic transistor including patterning the second conductive layer to leave a first portion of the second conductive layer over the remaining portion of the first metal layer and a second portion of the second conductive layer over the remaining portion of the dielectric layer.

2. The method of claim 1 , wherein the step of forming the first conductive layer comprises forming a first polysilicon layer and the step of forming the second conductive layer comprises forming a second polysilicon layer.

3. The method of claim 1 , wherein the step of forming the second conductive layer comprises forming a second metal layer.

4. The method of claim 3 , wherein the step of forming the second conductive layer further comprises forming a first polysilicon layer over the second metal layer.

5. The method of claim 3 , wherein the step of forming the second conductive layer is further characterized by the second metal layer being thicker than the first metal layer.

6. The method of claim 5 , wherein the step of forming the second conductive layer is further characterized by the first metal and the second metal layer having a same work function.

7. The method of claim 1 , wherein the step of forming the dielectric layer comprises forming a charge storage layer comprising a first insulating layer, a plurality of nanocrystals over the first insulating layer, and a second insulating layer around and over the plurality of nanocrystals.

8. The method of claim 1 , wherein the step of forming the NVM cell and the logic transistor further comprises patterning the remaining portion of the first conductive layer to form a floating gate.

9. The method of claim 1 , further comprising removing the gate dielectric from the logic region prior to forming the high-k dielectric.

10. A method of forming a logic transistor and a non-volatile memory cell, comprising:

forming a gate dielectric layer on the substrate;

depositing a first conductive layer over the gate dielectric layer;

patterning the first conductive layer to leave a portion of the first conductive layer;

forming a dielectric layer over the substrate after patterning the first conductive layer wherein the dielectric layer has a top insulating layer comprising silicon dioxide;

forming a silicon nitride layer over the dielectric layer;

patterning the silicon nitride layer and the dielectric layer to leave a portion of the dielectric layer and a portion of the silicon nitride layer over and extending around the portion of the first conductive layer;

depositing a high-k dielectric layer over the substrate after patterning the silicon nitride layer and the dielectric layer;

depositing a first metal layer over the high-k dielectric layer;

removing the first metal layer, the high-k dielectric layer, and the silicon nitride layer from over the dielectric layer to leave a portion of the dielectric layer and a portion of the first metal layer over the portion of the dielectric layer;

forming a second conductive layer over the substrate after removing the first metal layer, the high-k dielectric layer, and the silicon nitride layer from over the dielectric layer; and

forming the non-volatile memory cell and logic transistor including patterning the second conductive layer to leave a first portion of the second conductive layer over the portion of the first metal layer and a second portion of the second conductive layer over the portion of the dielectric layer.

11. The method of claim 10 , wherein the step of forming the first conductive layer comprises forming a first polysilicon layer and the step of forming the second conductive layer comprises depositing a second metal layer and depositing a second polysilicon layer directly on the second metal layer.

12. The method of claim 10 , wherein the step of forming the second conductive layer comprises depositing a polysilicon layer over the substrate including directly on the portion of the first metal layer and directly on the portion of the dielectric layer.

13. The method of claim 10 , wherein the step of forming the non-volatile memory comprises etching the portion of the first conductive layer to form a select gate and the step of forming the dielectric layer comprises forming a layer of nanocrystals.

14. A method of making a non-volatile memory cell and a logic transistor on a substrate, comprising:

forming a first gate dielectric comprising silicon oxide over the substrate;

forming a second gate dielectric of high-k material over the substrate spaced from the first gate dielectric;

forming a first portion of a first conductive layer over the first gate dielectric;

forming a first portion of a first metal layer on the second gate dielectric;

forming a dielectric layer over the first portion of the first conductive layer;

forming a first portion of a second metal layer over the first portion of the first metal layer;

forming a second portion of the second metal layer over the dielectric layer;

forming a first portion of a second conductive layer over the first portion of the second metal layer; and

forming a second portion of the second conductive layer over the second portion of the second metal layer.

15. The method of claim 14 , wherein the first metal layer and the second metal layer have the same work function.

16. The method of claim 14 , wherein the dielectric layer comprises a charge storage layer comprising a first insulating layer, a plurality of nanocrystals over the first insulating layer, and a second insulating layer around and over the plurality of nanocrystals.

17. The method of claim 14 , wherein the dielectric layer comprises a first oxide insulating layer, a silicon nitride insulating layer over the first oxide insulating layer, and a second oxide insulating layer over the silicon nitride insulating layer.

18. The method of claim 14 , wherein the first portion of the first conductive layer is a floating gate comprising polysilicon.

19. The method of claim 14 , wherein the second conductive layer comprises polysilicon.

Assignments (26)