Method and apparatus for testing a random number generator tester
View Patent ↗A method and apparatus for testing operation of a random number generator (RNG) testing circuit are provided. In accordance with at least one embodiment, a first RNG output value obtained from a RNG is stored in a first register. In response to activation of a test mode to simulate a faulty RNG, the first RNG output value is stored in a second register. The first RNG output value in the first register is compared to the first RNG output value in the second register. In response to the comparing, a RNG failure signal is provided at a RNG testing circuit output of the RNG testing circuit. In accordance with at least one embodiment, sequential and combinational logic can simulate a faulty RNG. Accordingly, simulation of a faulty RNG may be performed to test a RNG testing circuit even when the RNG is not faulty.
1. A method for testing operation of a random number generator (RNG) testing circuit comprising:
at a first time, storing a first RNG output value obtained from a RNG in a first register;
at a second time, in response to activation of a test mode to simulate a faulty RNG, storing the first RNG output value in a second register;
at a third time, comparing the first RNG output value in the first register to the first RNG output value in the second register; and
in response to the comparing, providing a RNG failure signal at a RNG testing circuit output of the RNG testing circuit.
2. The method of claim 1 wherein the second time occurs after the first time.
3. The method of claim 1 wherein the second time occurs before the first time.
4. The method of claim 1 wherein the second time occurs substantially simultaneously with the first time.
5. The method of claim 1 further comprising:
obtaining from a different source the first RNG output value to be stored in the second register, wherein the RNG is a deterministic RNG.
6. The method of claim 1 wherein the storing the RNG output value in the second register comprises:
causing the first RNG output value to be copied from the first register to the second register.
7. The method of claim 1 further comprising:
providing the RNG failure signal at a RNG testing circuit output of the RNG testing circuit in response to a software-writable memory bit being set to a first state.
8. A method comprising:
storing a first random number generator (RNG) output value of a properly operating RNG in a first register;
storing a second value in a second register;
comparing the first RNG output value in the first register to the second value in the second register and providing a comparator output signal at a comparator output;
receiving the comparator output signal and a software-writable value at a logic circuit; and
providing from the logic circuit a RNG failure signal at a RNG testing circuit output of the RNG testing circuit in response to a logical relationship of the comparator output signal and the software-writable value.
9. The method of claim 8 wherein the logic circuit causes the RNG failure signal to have a RNG failure signal value indicative of a RNG failure when the software-writable value has a first value regardless of a comparator output value of the comparator output signal.
10. The method of claim 8 wherein the logic circuit stores the software-writable value and performs a logical operation on the software-writable value and a comparator output value of the comparator output signal received from the comparator to produce the RNG failure signal.
11. A random number generator (RNG) testing circuit comprising:
a first register for storing a RNG output value of a RNG;
a second register comprising a test mode input adapted to cause the second register to store the RNG output value to simulate a faulty RNG; and
a comparator coupled to the first register and to the second register for comparing the RNG output value in the first register to the RNG output value in the second register while the RNG output value is stored in the first register and the second register and for providing a RNG failure signal at a RNG testing circuit output of the RNG testing circuit.
12. The RNG testing circuit of claim 11 wherein the second register is configured to store the RNG output value after the first register has stored the RNG output value.
13. The RNG testing circuit of claim 11 wherein the second register is configured to store the RNG output value before the first register has stored the RNG output value.
14. The RNG testing circuit of claim 11 wherein the second register is configured to store the RNG output value simultaneously with the first register storing the RNG output value.
15. The RNG testing circuit of claim 11 further comprising:
a processor distinct from the RNG, the processor coupled to the second register, the processor for calculating the RNG output value to be stored in the second register, wherein the RNG provides the RNG output value to be stored in the first register, wherein the RNG is a deterministic RNG.
16. The RNG testing circuit of claim 11 wherein the second register obtains the RNG output value stored in the second register from the first register.
17. The RNG testing circuit of claim 11 further comprising:
a memory for storing a software-writable memory bit, wherein the RNG testing circuit provides the RNG failure signal at the RNG testing circuit output in response to a software-writable memory bit being set to a first state.
18. A random number generator (RNG) testing circuit comprising:
a first register for storing a first RNG output value of a properly operating RNG;
a second register for storing a second value;
a comparator coupled to the first register and to the second register for comparing the first RNG output value in the first register to the second value in the second register and for providing a comparator output signal at a comparator output of the comparator; and
a logic circuit coupled to the comparator output for receiving the comparator output signal and a software-writable value and for providing a RNG failure signal at a RNG testing circuit output of the RNG testing circuit in response to a logical relationship of the comparator output signal and the software-writable value, the logic circuit comprising:
a sequential logic element; and
a combinational logic element coupled to the sequential logic element.
19. The RNG testing circuit of claim 18 wherein the logic circuit causes the RNG failure signal to have a RNG failure signal value indicative of a RNG failure when the software-writable value has a first value regardless of a comparator output value of the comparator output.
20. The RNG testing circuit of claim 18 wherein the sequential logic element stores the software-writable value and the combinational logic element performs a logical operation on the software-writable value received from the sequential logic element and a comparator output value of the comparator output signal received from the comparator to produce the RNG failure signal.