IP Library Granted Patent US 8,901,991
Granted Patent B2
US 8,901,991 · App. 13/848,348 · Granted Dec 2, 2014

Power monitoring circuitry

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,901,991
App. No.
13/848,348
Granted
Dec 2, 2014
Kind
B2
Abstract

Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.

Claims (27)

1. A monitoring circuit, comprising:

comparator circuitry configured to identify the greater between a first voltage value and a second voltage value, wherein the comparator circuitry includes a first inverter cross-coupled with a second inverter, the first inverter configured to receive the first voltage value and the second inverter configured to receive the second voltage value; and

selector circuitry coupled to the comparator circuitry, the selector circuitry configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the identified voltage value, wherein the one or more components include a first Schmitt trigger coupled to an output of the first inverter and a second Schmitt trigger coupled to an output of the second inverter.

2. The monitoring circuit of claim 1 , wherein the output of the first inverter is configured to be pulled up to the first voltage value and wherein the output of the second inverter is configured to be pulled down to a reference voltage value in response to the first voltage value being greater than the second voltage value.

3. The monitoring circuit of claim 1 , wherein the output of the first inverter is configured to be pulled down to a reference voltage value and wherein the output of the second inverter is configured to be pulled up to the second voltage value in response to the second voltage value being greater than the first voltage value.

4. The monitoring circuit of claim 1 , wherein the one or more components further include a first latch having a reset input ( R ) configured to receive an output of the first Schmitt trigger and a set input ( S ) configured to receive an output of the second Schmitt trigger.

5. The monitoring circuit of claim 4 , wherein the one or more components further include a second latch having a set input ( S ) configured to receive an output (Q) of the first latch and a reset input ( R ) configured to receive a complementary output ( Q ) of the first latch.

6. The monitoring circuit of the claim 5 , an output (Q) of the second latch configured to assume a logic high value in response to the first voltage value being greater than the second voltage value, and a complementary output ( Q ) of the second latch configured to assume a logic high value in response to the second voltage value being greater than the first voltage value.

7. The monitoring circuit of claim 6 , the output (Q) of the second latch configured to lower a trip point of the first inverter in response to the first voltage being greater than the second voltage.

8. The monitoring circuit of claim 6 , the complementary output ( Q ) of the second latch configured to lower a trip point of the second inverter in response to the second voltage being greater than the first voltage.

9. An electronic device, comprising:

a comparator circuit having a first inverter cross-coupled with a second inverter, the first inverter configured to receive a first voltage and the second inverter configured to receive a second voltage, wherein: (a) an output of the first inverter is configured to be pulled up to the first voltage and an output of the second inverter is configured to be pulled down to a reference voltage in response to the first voltage being greater than the second voltage, and (b) the output of the first inverter is configured to be pulled down to the reference voltage and the output of the second inverter is configured to be pulled up to the second voltage in response to the second voltage being greater than the first voltage;

a switching circuit coupled to the comparator circuit, the switching circuit configured to:

(a) provide the first voltage to one or more components within the comparator circuit in response to the first voltage being greater than the second voltage, and

(b) provide the second voltage to the one or more components within the comparator circuit in response to the second voltage being greater than the first voltage; and

a pulse generator circuit coupled to the comparator circuit, the pulse generator circuit configured to receive a refresh signal and to output a first pulse and a second pulse, the second pulse having a longer duration than the first pulse.

10. The electronic device of claim 9 , wherein the first and second inverters are configured to become decoupled from the reference voltage and the comparator circuit is configured to be reset during the first pulse.

11. The electronic device of claim 10 , wherein the first and second inverters are configured to have their respective regeneration times decreased during the second pulse.

12. The electronic device of claim 10 , wherein the first and second inverters are configured to be coupled to the reference voltage during a time between the end of the first pulse and the end of the second pulse.

13. The electronic device of claim 12 , wherein the comparator circuit is configured to latch according to a sign of a voltage difference between the first voltage and the second voltage.

14. A method, comprising:

receiving, via a comparator circuit, a first voltage value and a second voltage value, wherein the comparator circuit includes a first inverter cross-coupled with a second inverter, the first inverter configured to receive the first voltage value and the second inverter configured to receive the second voltage value;

identifying, via the comparator circuit, the largest between the first and second voltage values; and

powering one or more components within the comparator circuit with a supply voltage selected by a selector circuit, wherein the supply voltage corresponds to the identified voltage value, and wherein the one or more components include a first and a second Schmitt trigger, the first Schmitt trigger coupled to an output of the first inverter, and the second Schmitt trigger coupled to an output of the second inverter.

15. The method of claim 14 , further comprising periodically decoupling at least one of the first or second inverters within the comparator circuit from a ground voltage.

16. The method of claim 15 , further comprising periodically re-coupling at least one of the first or second inverters to the ground voltage to place the comparator circuit in a metastable condition.

17. The method of claim 14 , further comprising biasing one or more transistors using the identified voltage value.

Assignments (30)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030445/0581 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030445/0709 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 030445/0737 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2013
From: ZANETTA, PEDRO BARBOSA; NASCIMENTO, IVAN CARLOS RIBEIRO
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030060/0200 →