Embedded NVM in a HKMG process
View Patent ↗A process integration is disclosed for fabricating complete, planar non-volatile memory (NVM) cells ( 110 ) prior to the formation of high-k metal gate electrodes for CMOS transistors ( 212, 213 ) using a planarized dielectric layer ( 26 ) and protective mask ( 28 ) to enable use of a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.
1. A semiconductor fabrication process comprising:
providing a wafer comprising;
a plurality of nonvolatile memory cell gate structures formed over a substrate with one or more polysilicon layers, and
a plurality of sacrificial transistor gate structures formed over the substrate with the one or more polysilicon layers;
forming a dielectric layer having a substantially flat upper surface which exposes an upper surface of the plurality of sacrificial transistor gate structures;
forming a protective mask layer over the plurality of nonvolatile memory cell gate structures;
selectively removing the plurality of sacrificial transistor gate structures using the protective mask layer to protect the plurality of nonvolatile memory cell gate structures to form a plurality of gate electrode openings in the dielectric layer without removing the plurality of nonvolatile memory cell gate structures;
forming a metal layer in the plurality of gate electrode openings; and
polishing the metal layer down to be substantially coplanar with the plurality of nonvolatile memory cell gate structures to define a plurality of high-k metal gate electrodes in the plurality of gate electrode openings.
2. The semiconductor fabrication process of claim 1 , where providing the wafer comprises providing forming source/drain regions in the substrate which are in functional alignment with the plurality of nonvolatile memory cell gate structures and the plurality of sacrificial transistor gate structures.
3. The semiconductor fabrication process of claim 1 , where providing the wafer comprises:
forming the plurality of nonvolatile memory cell gate structures and a plurality of high voltage transistor gate structures over the substrate with one or more polysilicon layers; and
forming a plurality of CMOS sacrificial transistor gate structures over the substrate with one or more polysilicon layers.
4. The semiconductor fabrication process of claim 1 , where forming the dielectric layer comprises:
depositing a conformal oxide layer over the wafer to cover the plurality of nonvolatile memory cell gate structures and the plurality of sacrificial transistor gate structures, and
planarizing the conformal oxide layer with a chemical mechanical polish process to form the substantially flat upper surface.
5. The semiconductor fabrication process of claim 1 , where forming the protective mask layer comprises:
depositing a silicon nitride layer over the wafer to cover the dielectric layer; and
selectively etching the silicon nitride layer to expose the plurality of sacrificial transistor gate structures.
6. The semiconductor fabrication process of claim 1 , where selectively removing the plurality of sacrificial transistor gate structures comprises:
applying one or more poly etch processes to remove the one or more polysilicon layers from the plurality of sacrificial transistor gate structures; and
applying one or more dielectric etch processes to remove one or more gate dielectric layers from the plurality of sacrificial transistor gate structures, thereby exposing the substrate with the plurality of gate electrode openings in the dielectric layer.
7. The semiconductor fabrication process of claim 1 , where forming high-k metal gate electrodes comprises:
forming one or more high-k dielectric layers in the plurality of gate electrode openings in the dielectric layer using a dielectric material which has a dielectric constant value of 7.0 or greater; and
depositing one or more metal gate electrode layers over the one or more high-k dielectric layers in the plurality of gate electrode openings in the dielectric layer.
8. The semiconductor fabrication process of claim 7 , further comprising growing a thermal oxide interface layer on exposed substrate surfaces of the plurality of gate electrode openings before forming the one or more high-k dielectric layers in the plurality of gate electrode openings.
9. The semiconductor fabrication process of claim 1 , where selectively removing the plurality of sacrificial transistor gate structures comprises applying one or more poly etch processes to remove the one or more polysilicon layers to expose an underlying high-k gate dielectric layer in the plurality of gate electrode openings in the dielectric layer; and where forming the metal layer comprises depositing one or more metal gate electrode layers over the underlying high-k gate dielectric layer in the plurality of gate electrode openings.
10. The semiconductor fabrication process of claim 1 , where the plurality of nonvolatile memory cell gate structures comprises a plurality of split-gate flash memory cell gate structures.