IP Library Granted Patent US 9,170,974
Granted Patent B2
US 9,170,974 · App. 13/775,330 · Granted Oct 27, 2015

Methods and systems for interconnecting host and expansion devices within system-in-package (SiP) solutions

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Quick Facts
Patent No.
US 9,170,974
App. No.
13/775,330
Granted
Oct 27, 2015
Kind
B2
Abstract

Methods and systems are disclosed for interconnecting die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance. In addition, level shift circuitry can be utilized within expansion devices to allow for standardized interconnect signals and supply voltages to be provided by DTDP host devices to DTDP expansion devices.

Claims (66)

1. A die-to-die port (DTDP) system, comprising:

a DTDP expansion device within a first integrated circuit; and

a DTDP host device within a second integrated circuit;

the DTDP expansion device within the first integrated circuit, comprising:

an expansion circuit block configured to provide expansion functionality for the DTDP host device; and

a circuit interconnection block coupled to the expansion circuit block and configured to provide interconnectivity to the DTDP host device; and

the DTDP host device within the second integrated circuit, comprising:

port interconnect circuitry having a plurality of ports and being configured to provide communication between the plurality of ports, the port interconnect circuitry being further configured to cause the expansion functionality to appear to be resident on the DTDP host device;

a master circuit block coupled to the port interconnect circuitry and configured to provide functionality for the DTDP host device; and

a circuit interconnection block coupled to the port interconnect circuitry and being configured to provide interconnectivity to the DTDP expansion device using at least one of the plurality of ports;

wherein the DTDP host device is configured to provide at least one voltage supply signal to the DTDP expansion device during operation through the circuit interconnection blocks for the DTDP expansion device and DTDP host device.

2. The DTDP system of claim 1 , wherein the first integrated circuit and the second integrated circuit are packaged within a single package to form a system-in-package (SiP) device.

3. The DTDP system of claim 1 , wherein the port interconnect circuitry comprises crossbar interconnect fabric circuitry.

4. The DTDP system of claim 1 , wherein the DTDP expansion device further comprises port interconnect circuitry having a plurality of ports with at least one port being coupled to the expansion circuit block, and wherein the circuit interconnection block for the DTDP expansion device is configured to provide interconnectivity to the DTDP host device using at least one of the plurality of ports.

5. The DTDP system of claim 1 , wherein the circuit interconnection block for the DTDP host device and the circuit interconnection block for the DTDP expansion device comprise copper pillar connectors.

6. The DTDP system of claim 1 , wherein the DTDP expansion device comprises a slave device, and wherein one port on the port interconnect circuitry for the DTDP host device is used to communicate with a port on the DTDP expansion device.

7. The DTDP system of claim 1 , wherein the DTDP expansion device comprises a master/slave device, and wherein two ports on the port interconnect circuitry for the DTDP host device are used to communicate with a master port and a slave port on the DTDP expansion device.

8. The DTDP system of claim 1 , wherein at least one of DTDP expansion device identity information, DTDP host device identity information, clock information, or signal level information is configured to be communicated between the DTDP expansion device and the DTDP host device during start-up or reset.

9. The DTDP system of claim 1 , wherein the DTDP host device is further configured to provide at least one interconnect signal to the DTDP expansion device during operation through the circuit interconnection blocks for the DTDP expansion device and the DTDP host device.

10. The DTDP system of claim 1 , wherein the DTDP expansion device further comprises regulator circuitry configured to adjust a voltage level for the at least one voltage supply signal for use within the DTDP expansion device.

11. The DTDP system of claim 1 , wherein the DTDP host device further comprises regulator circuitry configured to adjust the at least one voltage supply signal for use by the DTDP expansion device.

12. A die-to-die port (DTDP) system, comprising:

a DTDP expansion device within a first integrated circuit; and

a DTDP host device within a second integrated circuit;

the DTDP expansion device within the first integrated circuit, comprising:

an expansion circuit block configured to provide expansion functionality for the DTDP host device; and

a circuit interconnection block coupled to the expansion circuit block and configured to provide interconnectivity to the DTDP host device; and

the DTDP host device within the second integrated circuit, comprising:

port interconnect circuitry having a plurality of ports and being configured to provide communication between the plurality of ports, the port interconnect circuitry being further configured to cause the expansion functionality to appear to be resident on the DTDP host device;

a master circuit block coupled to the port interconnect circuitry and configured to provide functionality for the DTDP host device; and

a circuit interconnection block coupled to the port interconnect circuitry and being configured to provide interconnectivity to the DTDP expansion device using at least one of the plurality of ports;

wherein the DTDP host device is further configured to provide at least one interconnect signal to the DTDP expansion device during operation through the circuit interconnection blocks for the DTDP expansion device and the DTDP host device; and

wherein the DTDP expansion device further comprises level shift circuitry configured to adjust a voltage level for the at least one interconnect signal for use within the DTDP expansion device.

13. A die-to-die port (DTDP) system, comprising:

a DTDP expansion device within a first integrated circuit; and

a DTDP host device within a second integrated circuit;

the DTDP expansion device within the first integrated circuit, comprising:

an expansion circuit block configured to provide expansion functionality the DTDP host device; and

a circuit interconnection block coupled to the expansion circuit block and configured to provide interconnectivity to the DTDP host device; and

the DTDP host device within the second integrated circuit, comprising:

port interconnect circuitry having a plurality of ports and being configured to provide communication between the plurality of ports, the port interconnect circuitry being further configured to cause the expansion functionality to appear to be resident on the DTDP host device;

a master circuit block coupled to the port interconnect circuitry and configured to provide functionality for the DTDP host device; and

a circuit interconnection block coupled to the port interconnect circuitry and being configured to provide interconnectivity to the DTDP expansion device using at least one of the plurality of ports;

wherein the DTDP host device is further configured to provide at least one interconnect signal to the DTDP expansion device during operation through the circuit interconnection blocks for the DTDP expansion device and DTDP host device; and

wherein the DTDP host device further comprises level shift circuitry configured to adjust a voltage level for the at least one interconnect signal for use within the DTDP expansion device.

14. A method for operating a die-to-die port (DTDP) system, comprising:

providing expansion functionality for a DTDP host device using an expansion circuit block within a DTDP expansion device, the DTDP expansion device being within a first integrated circuit, and the DTDP host device being within a second integrated circuit;

utilizing a circuit interconnection block within the DTDP expansion device to provide interconnectivity to the DTDP host device;

providing host functionality using the DTDP host device;

utilizing port interconnect circuitry within the DTDP host device to provide connectivity between a plurality of ports within the DTDP host device and to cause the expansion functionality to appear to be resident on the DTDP host device;

communicating between a master circuit block and the port interconnect circuitry within the DTDP host device to provide functionality for the DTDP host device; and

utilizing a circuit interconnection block within the DTDP host device to provide interconnectivity to the DTDP expansion device using at least one of the plurality of ports; and

further comprising providing at least one voltage supply signal from the DTDP host device to the DTDP expansion device during operation.

15. The method of claim 14 , wherein the first integrated circuit and the second integrated circuit are packaged within a single package to form a system-in-package (SiP) device.

16. The method of claim 14 , wherein the DTDP expansion device comprises a slave device, and further comprising using one port for the port interconnect circuitry on the DTDP host device to communicate with a port on the DTDP expansion device.

17. The method of claim 14 , wherein the DTDP expansion device comprises a master/slave device, and further comprising using two ports for the port interconnect circuitry on the DTDP host device to communicate with a master port and a slave port on the DTDP expansion device.

18. The method of claim 14 , further comprising communicating at least one of DTDP expansion device identity information, DTDP host device identity information, clock information, or signal level information between the DTDP expansion device and the DTDP host device during start-up or reset.

19. The DTDP system of claim 14 , further comprising using regulator circuitry to adjust a voltage level for the at least one voltage supply signal.

20. A method for operating a die-to-die port (DTDP) system, comprising:

providing expansion functionality for a DTDP host device using an expansion circuit block within a DTDP expansion device, the DTDP expansion device being within a first integrated circuit, and the DTDP hose device being within a second integrated circuit;

utilizing a circuit interconnection block within the DTDP expansion device to provide interconnectivity to the DTDP host device;

providing host functionality using the DTDP host device;

utilizing port interconnect circuitry within the DTDP host device to provide connectivity between a plurality of ports within the DTDP host device and to cause the expansion functionality to appear to be resident on the DTDP host device;

communicating between a master circuit block and the port interconnect circuitry within the DTDP host device to provide functionality for the DTDP host device; and

utilizing a circuit interconnection block within the DTDP host device to provide interconnectivity to the DTDP expansion device using at least one of the plurality of ports; and

further comprising using level shift circuitry to adjust a voltage level for at least one interconnect signal communicated between the DTDP host device to the DTDP expansion device during operation.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2013
From: MILLER, GARY L.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029864/0938 →