Multiport memory with matching address control
View Patent ↗In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a third and fourth bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic and to the third bit line pair via second switching logic, and a second data line pair is coupled to the second bit line pair via third switching logic and to the fourth bit line pair via fourth switching logic. If a match exists between at least portions of a first and second access address, a state of the third and forth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second data line pair.
1. A multiple port static random access memory (SRAM), comprising:
a first word line and a second word line of a plurality of word lines;
a first bit line pair, a second bit line pair, a third bit line pair, and a fourth bit line pair of a plurality of bit line pairs;
an array of bit cells coupled to the plurality of word lines and the plurality of bit line pairs, wherein the array of bit cells comprises:
a first bit cell having a first storage latch, and coupled to the first word line and the first bit line pair to access a first storage latch, and coupled to the second word line and the second bit line pair to access the first storage latch; and
a second bit cell having a second storage latch, and coupled to the first word line and the third bit line pair to access a second storage latch, and coupled to the second word line and the fourth bit line pair to access the second storage latch;
a first read/write data line pair of a first plurality of read/write data line pairs for accessing the array of bit cells, and a second read/write data line pair of a second plurality of read/write data line pairs for accessing the array of bit cells, wherein:
the first read/write data line pair is coupled to the first bit line pair via first switching logic and coupled to the third bit line pair via second switching logic; and
the second read/write data line pair is coupled to the second bit line pair via third switching logic and coupled to the fourth bit line pair via fourth switching logic; and
a match detector which provides a match indicator based on whether at least a portion of a first access address matches at least a portion of a second access address, and in response to the match indicator indicating a match, a state of the third and forth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second read/write data line pair.
2. The multiple port SRAM of claim 1 , further comprising:
coupling circuitry, wherein, in response to the match indicator indicating a match, the coupling circuitry couples true data lines of the first and second read/write data line pairs with each other and couples complementary data lines of the first and second read/write data line pairs with each other.
3. The multiple port SRAM of claim 2 , wherein the coupling circuitry comprises:
a first transistor having a first current electrode connected to the true data line of the first read/write data line pair, a second current electrode connected to the true data line of second read/write data line pair, and control electrode coupled to receive the match indicator; and
a second transistor having a first current electrode connected to the complementary data line of the first read/write data line pair, a second current electrode connected to the complementary data line of second read/write data line pair, and control electrode coupled to receive the match indicator.
4. The multiple port SRAM of claim 1 , further comprising:
column decode circuitry which provides a first column decode output in response to the first access address and provides a second column decode output in response to the second access address.
5. The multiple port SRAM of claim 4 , wherein, in response to the match indicator not indicating a match, the state of the first and second switching logic is determined by the first column decode output such that one of the first and second bit cells is accessed by the first read/write data line pair, and the state of the third and fourth switching logic is determined by the second column decode output such that one of the first and second bit cells is access by the second read/write data line pair.
6. The multiple port SRAM of claim 4 , wherein, in response to the match indicator indicating a match, the state of the first and second switching logic is determined by the first column decode output and the state of the third and fourth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second data line pair, regardless of a value of the second column decode output.
7. The multiple port SRAM of claim 1 , further comprising:
first read/write circuitry coupled to the first data line pair such that when the first word line is selected, the first data line pair accesses one of the first or second bit cell based on a state of the first and second switching logic; and
second read/write circuitry coupled to the second data line pair such that, when the second word line is selected and the match indicator does not indicate a match, the second data line pair accesses one of the first or second bit cell based on a state of the third and fourth switching logic.
8. The multiple port SRAM of claim 1 , further comprising:
first row decode circuitry coupled to a first subset of the plurality of word lines, including the first word line, wherein the first row decode circuitry activates a word line of the first subset based on the first access address; and
second row decode circuitry coupled to a second subset of the plurality of word lines, including the second word line, wherein the first subset and the second subset are mutually exclusive.
9. The multiple port SRAM of claim 8 , wherein:
when the match indicator does not indicate a match, the second row decode circuitry activates a word line of the second subset based on the second access address, and
when the match indicator indicates a match, the second row decode circuitry is disabled, in which the second word line is disabled.
10. The multiple port SRAM of claim 1 , wherein the at least a portion of the first access address is characterized as a first row address derived from the first access address, and the at least a portion of the second access address is characterized as a second row address derived from the second access address.
11. The multiple port SRAM of claim 1 , wherein, when the match indicator does not indicate a match, the first plurality of read/write data lines access a first set of bit cells of the array of bit cells is response to the first access address, and the second plurality of read/write data lines access a second set of bit cells of the array of bit cells, mutually exclusive of the first set of bit cell, in response to the second access address.
12. The multiple port SRAM of claim 11 , wherein the access of the first plurality of read/write data lines occurs simultaneously with the access of the second plurality of read/write data lines.
13. A method for accessing a multiple port static random access memory (SRAM) having a plurality of word lines, a plurality of bit line pairs, and a plurality of bit cells coupled to the plurality of word lines and the plurality of bit line pairs, wherein each of the plurality of bit cells is coupled to a first bit line pair and a second bit line pair of the plurality of bit line pairs and a first word line and a second word line of the plurality of word lines, the method comprising:
providing a first access address and a second access address to the multiple port SRAM;
providing a match indicator based on a comparison between at least a portion of the first access address and at least a portion of the second access address;
if the match indicator indicates a match:
deactivating the second word line for each bit cell of the plurality of bit cells; and
for each bit cell selected by the first access address, using a first read/write data line pair of the multiple port SRAM to access the bit cell using the first bit line pair and first word line, while decoupling the second bit line pair of the bit cell from a second read/write data line pair of the multiple port SRAM.
14. The method of claim 13 , wherein if the match indicator indicates a match, the method further comprises:
coupling a true read/write data line of the first read/write data line pair to a true read/write data line of the second read/write data line pair; and
coupling a complementary read/write data line of the first read/write data line pair to a complementary read/write data line of the second read/write data line pair.
15. The method of claim 13 , wherein, if the match indicator does not indicate a match, the method comprises:
for each bit cell selected by the first access address, using the first read/write data line pair to perform a read or write access to the bit cell; and
for each bit cell selected by the second access address, using the second read/write data line pair to perform a read or write access to the bit cell.
16. A multiple port static random access memory (SRAM), comprising:
a first bit cell having a first storage latch, and coupled to a first word line, a first true bit line, and a first complementary bit line to access the storage latch, and coupled to a second word line, a second true bit line, and a second complementary bit line to access the first storage latch;
a second bit cell having a second storage latch, and coupled to the first word line, a third true bit line, and a third complementary bit line to access the second storage latch, and coupled to the second word line, a fourth true bit line, and a fourth complementary bit line to access the second storage latch;
a first data line pair, wherein the first true bit line and first complementary bit line and third bit line and third complementary bit line are coupled to the first data line pair via first column decode circuitry that is responsive to a first access address;
a second data line pair, wherein the second true bit line and the second complementary bit line and fourth bit line and fourth complementary bit line are coupled to the second data line pair via second column decode circuitry that is responsive to a second access address;
a match detector which provides a match indicator based on whether a first row address derived from the first access address matches a second row address derived from the second access address; and
decoupling logic which, in response to the match indicator indicating a match, overrides the second column decode circuitry such that second true bit line and second complementary bit line remains decoupled from the second data line pair and the fourth true bit line and the fourth complementary bit line remains decoupled from the second data line pair.
17. The multiple port SRAM of claim 16 , further comprising:
coupling circuitry coupled between the first data line pair and the second data line pair, wherein, in response to the match indicator indicating a match, the coupling circuitry couples true data lines of the first and second read/write data line pairs with each other and short complementary data line of the first and second read/write data line pairs with each other.
18. The multiple port SRAM of claim 16 , wherein, in response to the match indicator not indicating a match, the first column decode circuitry selects either the first true and complementary bit lines or the third true and complementary bit lines to couple to the first data line pair based on the first access address, and the second column decode circuitry selects either the second true and complementary bit line or the fourth true and complementary bit lines to couple to the second data line pair based on the second access address.
19. The multiple port SRAM of claim 16 , further comprising:
first read/write circuitry coupled to the first data line pair such that when the first word line is selected, the first data line pair can read data from or write data to one of the first or second bit cell; and
second read/write circuitry coupled to the second data line pair such that, when the second word line is selected and the match indicator does not indicate a match, the second data line pair can read data from or write data to one of the first or second bit cell.
20. The multiple port SRAM of claim 16 , further comprising:
first row decode circuitry coupled to the first word line, wherein the first row decode circuitry selective activates the first word line based on the first access address; and
second row decode circuitry coupled to the second word line, wherein:
when the match indicator indicates a match, the second row decode circuitry is deactivated so as to deactivate the second word line, regardless of a value of the second access address; and
when the match indicator does not indicate a match, the second row decode circuitry selectively activates the second word line based on the second access address.