Integrated circuit device, data storage array system and method therefor
View Patent ↗An integrated circuit device comprises a data storage array controller for providing data storage array functionality for at least one data storage array. The data storage array controller comprises an address window controller arranged to receive at least one data storage device access command, and upon receipt of the at least one data storage device access command the address window controller is arranged to compare a target address of the at least one data storage device access command to an address window for a target storage device of the at least one data storage device access command, and if the target address is outside of the address window for the target storage device, block the at least one data storage device access command.
1. An integrated circuit device comprising:
a data storage array controller comprising an address window controller to receive a data storage device access command, to compare a first target address of the data storage device access command to a first address window for a first target storage device of the data storage device access command, and, if the first target address is outside of the first address window, to block the data storage device access command, substitute pseudo data for data corresponding to the first target address of the first target storage device, and initiate data recovery to recover data stored at the first target address of the first target storage device using the pseudo data to re-compute recovery information, wherein the first target storage device is one of a plurality of data storage devices of a data storage array, and each of the plurality of data storage devices has a different size, wherein the address window controller configures address windows for each of the plurality of data storage devices based on each of the different sizes.
2. The integrated circuit device of claim 1 wherein, upon receipt of a data storage device read command, the address window controller is further to compare a second target address of the data storage device read command to a second address window for a second target storage device of the data storage device read command, and if the second target address is outside of the second address window for the second target storage device, to substitute the pseudo data for data to be read for that data storage device read command, wherein the second address window is associated with a second size of the second target storage device.
3. The integrated circuit device of claim 2 wherein the data storage array controller further comprises a command decoder to receive an array access command, and upon receipt of the array access command to generate the data storage device access command in accordance with the received array access command.
4. The integrated circuit device of claim 3 wherein the data storage array controller further comprises a memory access module to receive the data storage device access command, and to perform an access operation on the data storage array in accordance with the data storage device access command.
5. The integrated circuit device of claim 4 wherein the address window controller is operably coupled between the command decoder and the memory access module such that the data storage device access command from the command decoder is conveyed to the memory access module via the address window controller.
6. The integrated circuit device of claim 4 wherein the data storage array controller further comprises a data manipulation module to perform data manipulation in accordance with the array access command, and the memory access module is further to make available to the data manipulation module data read from the data storage array in accordance with the data storage device read command.
7. The integrated circuit device of claim 6 wherein the address window controller is further to make available to the data manipulation module the pseudo data in place of data to be read from the data storage array if the second target address for the data to be read from the second target storage device is outside of the second address window for the second target storage device.
8. The integrated circuit device of claim 6 wherein the memory access module is further to perform read operations from the data storage array in accordance with the data storage device read command, and to load read data resulting from such read operations into a buffer accessible to the data manipulation module.
9. The integrated circuit device of claim 8 wherein the address window controller is further configured to load the pseudo data into the buffer accessible to the data manipulation module in place of data to be read from the data storage array if the second target address for the data to be read from the second target storage device is outside of the second address window for the second target storage device.
10. The integrated circuit device of claim 6 wherein the data manipulation module is further to perform, on data made available there to, in accordance with the array access command, one from a group consisting of: data protection; code generation; data recovery; data mirroring; data striping; and data redundancy.
11. The integrated circuit device of claim 3 wherein the address window controller is operably coupled to an address window register arranged to store address window information, and upon receipt of the data storage device access command from the command decoder, to store the first address window to the address window register.
12. The integrated circuit device of claim 11 wherein the address window controller is arranged to:
identify the first target storage device of the data storage device access command;
retrieve the address window information corresponding to the identified target storage device from the address window register;
compare the first target address of the data storage device access command to the retrieved address window information; and
if the first target address is outside of the address window for the first target storage device, block the at least one data storage device access command.
13. The integrated circuit device of claim 11 wherein the address window register comprises a configurable memory element capable of having its contents configured by a device external to the data storage array controller.
14. A data storage array system comprising:
a data storage array controller comprising an address window controller to receive a data storage device access command, and upon receipt of the data storage device access command, to compare a target address of the data storage device access command to an address window for a target storage device of the data storage device access command and if the target address is outside of the address window for the target storage device, to block the data storage device access command, substitute pseudo data for data corresponding to the target address of the target storage device, and initiate data recovery to recover data stored at the target address of the target storage device using the pseudo data to re-compute recovery information, wherein the target storage device is one of a plurality of data storage devices of a data storage array, and each of the plurality of data storage devices has a different size, wherein the address window controller configures address windows for each of the plurality of data storage devices based on each of the different sizes.
15. The data storage array system of claim 14 wherein the data storage array system comprises a signal processing module operably coupled to the data storage array controller, the signal processing module to provide array access commands to the data storage array controller.
16. The data storage array system of claim 15 wherein the address window controller is operably coupled to an address window register, the address window register to store address window information, and the signal processing module is further to configure the address window information within the address window register.
17. The data storage array system of claim 16 wherein, upon determination that a data storage device within the data storage array has become unavailable, the signal processing module is further to configure a null address window for the unavailable data storage device.
18. A method for providing data storage array functionality for a data storage array, the method comprising:
receiving a data storage device access command for performing an access operation with the data storage array;
comparing a target address of the data storage device access command to an address window for a target storage device of the data storage device access command, wherein the target storage device is one of a plurality of data storage devices, and each of the plurality of data storage devices has a different size, wherein the address window controller configures address windows for each of the plurality of data storage devices based on each of the different sizes;
if the target address is outside of the address window for the target storage device, blocking the data storage device access command;
substituting pseudo data for data corresponding to the target address of the target storage device; and
initiating data recovery to recover data stored at the target address of the target storage device using the pseudo data to re-compute recovery information.
19. The method of claim 18 further comprising:
providing, by a signal processing module coupled to a data storage array controller, array access commands to the data storage array controller.
20. The method of claim 19 further comprising:
storing, by an address window register coupled to an address window controller, address window information; and
configuring, by the signal processing module, the address window information within the address window register.