IP Library Granted Patent US 8,754,521
Granted Patent B1
US 8,754,521 · App. 13/799,031 · Granted Jun 17, 2014

Semiconductor device assembly having a heat spreader

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Quick Facts
Patent No.
US 8,754,521
App. No.
13/799,031
Granted
Jun 17, 2014
Kind
B1
Abstract

A packaged semiconductor device includes a package substrate, a semiconductor die on the package substrate, an encapsulant over the semiconductor die and package substrate, and a heat spreader having a pedestal portion and an outer portion surrounding the pedestal portion. The encapsulant includes an opening within a perimeter of the semiconductor die. The bottom surface of the pedestal portion of the heat spreader faces the top surface of the semiconductor die, wherein a first portion of the opening and at least a portion of the encapsulant is between the bottom surface of the pedestal portion and the semiconductor die.

Claims (32)

1. A packaged semiconductor device, comprising:

a package substrate;

a semiconductor die on the package substrate;

an encapsulant over the semiconductor die and package substrate, wherein the encapsulant comprises a plurality of openings within a perimeter of the semiconductor die, wherein each opening of the plurality of openings comprises a first portion between the bottom surface of the pedestal portion and the semiconductor die and a second portion outside a perimeter of the bottom surface of the pedestal portion and inside the perimeter of the semiconductor die;

a heat spreader having a pedestal portion and an outer portion surrounding the pedestal portion, wherein a bottom surface of the pedestal portion faces the top surface of the semiconductor die, wherein a first portion of the opening and at least a portion of the encapsulant is between the bottom surface of the pedestal portion and the semiconductor die.

2. The packaged semiconductor device of claim 1 , wherein a thickness of the encapsulant between the bottom surface of the pedestal and the semiconductor die is less than a thickness of the encapsulant outside a perimeter of the bottom surface of the pedestal portion and inside a perimeter of the semiconductor die.

3. The packaged semiconductor device of claim 1 , further comprising:

an interface material within the plurality of openings.

4. The packaged semiconductor device of claim 1 , wherein one of the openings comprises a plurality of protrusions extending from a perimeter of the opening onto a top surface of the semiconductor die, wherein each of the plurality of protrusions is between the bottom surface of the pedestal portion of the heat spreader and the semiconductor die.

5. The packaged semiconductor device of claim 1 , wherein the heat spreader comprises an outer portion surrounding the pedestal portion, wherein the outer portion is thinner than the pedestal portion.

6. The packaged semiconductor device of claim 1 , wherein the heat spreader comprises an outer portion surrounding the pedestal portion, wherein the bottom surface of the pedestal portion is at a different elevation than a bottom surface of the outer portion.

7. The packaged semiconductor device of claim 1 , wherein a shortest distance between the bottom surface of the pedestal portion of the heat spreader and the top surface of the semiconductor die is less than 80 microns.

8. A packaged semiconductor device, comprising:

a package substrate;

a semiconductor die on the package substrate;

an encapsulant over the semiconductor die and package substrate, wherein the encapsulant comprises:

an opening having a perimeter located within a perimeter of the semiconductor die, and

a plurality of protrusions within the opening which extend from a perimeter of the opening onto a top surface of the semiconductor die; and

a heat spreader having a pedestal portion and an outer portion surrounding the pedestal portion, wherein the pedestal portion is over the semiconductor die and wherein the plurality of protrusions and at least a portion of the opening are between the pedestal portion and the semiconductor die.

9. The packaged semiconductor device of claim 8 , further comprising:

an interface material within the opening, between the semiconductor die and the pedestal portion of the heat spreader.

10. The packaged semiconductor device of claim 8 , wherein a bottom surface of the pedestal portion faces the top surface of the semiconductor die, and wherein at least a portion of the perimeter of the opening is located outside a perimeter of a bottom surface of the pedestal portion of the heat spreader and inside the perimeter of the semiconductor die.

11. The packaged semiconductor device of claim 8 , wherein a thickness of the encapsulant between the bottom surface of the pedestal and the semiconductor die is less than a thickness of the encapsulant outside a perimeter of the bottom surface of the pedestal portion.

12. The packaged semiconductor device of claim 8 , wherein a first protrusion of the plurality of protrusions extends a full width of the opening.

13. The packaged semiconductor device of claim 8 , wherein the heat spreader comprises an outer portion surrounding the pedestal portion, wherein the outer portion is thinner than the pedestal portion.

14. The packaged semiconductor device of claim 8 , wherein the pedestal portion is downset relative to the outer portion such that the inner portion contacts interface material over the semiconductor die, and the outer portion contacts adhesive material over the encapsulant.

15. The packaged semiconductor device of claim 8 , wherein a shortest distance between the bottom surface of the pedestal portion of the heat spreader and the top surface of the semiconductor die is less than 80 microns.

16. A method for forming a packaged semiconductor device, comprising:

forming an encapsulant over a semiconductor die and a package substrate, wherein the semiconductor die is mounted onto the packaged substrate, and wherein the encapsulant comprises an opening which exposes a top surface of the semiconductor die and the opening comprises a plurality of protrusions extending from a perimeter of the opening onto a top surface of the semiconductor die, wherein each of the plurality of protrusions is between the bottom surface of the pedestal portion of the heat spreader and the semiconductor die;

applying an interface material to the top surface of the semiconductor die within the opening; and

positioning a pedestal portion of a heat spreader to contact the interface material, wherein a first portion of the opening and at least a portion of the encapsulant is between a bottom surface of the pedestal portion and the semiconductor die.

17. The method of claim 16 , wherein a thickness of the encapsulant between the bottom surface of the pedestal and the semiconductor die is less than a thickness of the encapsulant outside a perimeter of the bottom surface of the pedestal portion and inside a perimeter of the semiconductor die.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2013
From: CARPENTER, BURTON J.; HIGGINS, LEO M., III; YUAN, YUAN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 030904/0887 →