System and method for dynamically migrating stash transactions
View Patent ↗A system and method for dynamically migrating stash transactions include first and second processing cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), and an operating system (OS) scheduler. The first core executes a first thread associated with a frame manager. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers to indicate scheduling-out and scheduling-in of the first thread from the first core and to the second core. The STMMU uses the pre-empt notifiers to enable dynamic stash transaction migration.
1. A system for migrating at least one stash transaction between a plurality of processor cores of a multicore processor system, wherein each of the plurality of cores includes a cache register, the system comprising:
a main memory for storing an input/output memory management unit (IOMMU) mapping table that includes a mapping between a logical input/output (I/O) device number (LIODN) corresponding to an I/O device and a corresponding stash transaction destination identification (ID), wherein the stash transaction destination ID includes a cache register ID associated with a cache register of one of the cores of the plurality of cores;
a stash transaction migration management unit (STMMU), coupled to the main memory, for determining a first core ID of a first core that executes a first thread associated with a first I/O device when the first thread is scheduled-out from the first core, wherein the first I/O device has a corresponding first stash transaction destination ID stored in the IOMMU mapping table, determining a second core ID of a second core that executes the first thread after the first thread is scheduled-in, comparing the first and second core IDs, updating a stash transaction destination ID field of the IOMMU mapping table corresponding to the first I/O device when the first and second core IDs are different to replace the first stash transaction destination ID with a second stash transaction destination ID, wherein the stash transaction destination ID field for the first I/O device stores the first stash transaction destination ID, and updating a second cache register ID associated with a cache register of the second core when the first and second core IDs are different to replace the second cache register ID with a first cache register ID associated with a cache register of the first core;
a frame manager for generating a first data frame, initiating a direct memory access (DMA) transaction for storing the first data frame in an external buffer of the main memory, and initiating the at least one stash transaction; and
an IOMMU, coupled to the main memory, the frame manager, and the plurality of cores, for validating the DMA transaction initiated by the frame manager using a LIODN of the frame manager and determining a stash destination for the at least one stash transaction by accessing the IOMMU mapping table.
2. The system of claim 1 , wherein the STMMU is connected to an operating system (OS) scheduler for receiving pre-empt notifiers generated when the first thread is scheduled-in and scheduled-out.
3. The system of claim 2 , wherein the STMMU determines the first and second core IDs using the pre-empt notifiers generated by the OS scheduler.
4. The system of claim 3 , wherein the IOMMU validates the DMA transaction by searching for an entry in the IOMMU mapping table corresponding to the LIODN of the frame manager.
5. The system of claim 4 , wherein the IOMMU is coupled to the plurality of cores and the main memory by way of a system bus.
6. The system of claim 4 , wherein the STMMU executes in at least one of the plurality of cores.
7. The system of claim 4 , further comprising a queue manager, coupled to the frame manager, for broadcasting the at least one stash transaction to the plurality of cores.
8. A method for migrating at least one stash transaction between a plurality of processor cores of a multicore processor system using an input/output memory management unit (IOMMU) mapping table, wherein the IOMMU mapping table includes a mapping between an input/output (I/O) device and a corresponding stash transaction destination identification (ID), wherein the I/O device transmits a data frame to at least one core of the plurality of cores, and wherein the stash transaction destination ID includes a cache register ID associated with a corresponding core, the method comprising:
determining a first core ID corresponding to a first core of the plurality of cores that executes a first thread associated with a first I/O device when the first thread is scheduled-out from the first core, wherein the first I/O device has a corresponding first stash transaction destination ID stored in the IOMMU mapping table, and wherein the first stash transaction destination ID includes a first cache register ID associated with a cache register of the first core;
determining a second core ID corresponding to a second core that executes the first thread after the first thread is scheduled-in;
comparing the first and second core IDs;
updating the IOMMU mapping table corresponding to the first I/O device when the first and second core IDs are different to replace the first stash transaction destination ID with a second stash transaction destination ID, wherein the second stash transaction destination ID includes a second cache register ID associated with a cache register of the second core;
initiating the at least one stash transaction that corresponds to a first data frame received from the first I/O device;
broadcasting the at least one stash transaction to the plurality of cores; and
storing the first data frame in the cache register of the second core.
9. The method of claim 8 , wherein the first thread is scheduled-in and scheduled-out by an operating system (OS) scheduler.
10. The method of claim 9 , further comprising generating pre-empt notifiers when the first thread is scheduled-in and scheduled-out by the OS scheduler.
11. The method of claim 8 , wherein the IOMMU mapping table stores a mapping between a logical I/O device number (LIODN) corresponding to the at least one I/O device and the stash transaction destination ID.
12. The method of claim 8 , further comprising initiating a direct memory access (DMA) transaction for storing the first data frame in an external buffer of the main memory by the frame manager.
13. The method of claim 12 , further comprising validating the DMA transaction by an IOMMU by searching for an entry in the IOMMU mapping table corresponding to a LIODN of the first I/O device.
14. The method of claim 8 , further comprising updating the second cache register ID when the first and second core IDs are different to replace the second cache register ID with the first cache register ID.
15. The method of claim 8 , wherein the at least one stash transaction is initiated and broadcasted by a queue manager.
16. The method of claim 8 , wherein updating the IOMMU mapping table includes updating a stash transaction destination ID field by a stash transaction migration management unit (STMMU) corresponding to the first I/O device that stores the first stash transaction destination ID.
17. The method of claim 8 , wherein the first and second core IDs corresponding to the first and second cores, respectively, are determined by the STMMU when the first thread is scheduled-out and scheduled-in.
18. A method for migrating at least one stash transaction between a plurality of processor cores in a multicore processing system using an input/output memory management unit (IOMMU) mapping table, wherein the IOMMU mapping table includes a mapping between an input/output (I/O) device and a corresponding stash transaction destination identification (ID), wherein the I/O device transmits a data frame to at least one core of the plurality of cores, and wherein the stash transaction destination ID includes a cache register ID associated with a corresponding core, the method comprising:
determining a first core ID corresponding to a first core of the plurality of cores that executes a first thread associated with a first I/O device when the first thread is scheduled-out from the first core, wherein the first I/O device has a corresponding first stash transaction destination ID stored in the IOMMU mapping table, and wherein the first stash transaction destination ID includes a first cache register ID associated with a cache register of the first core;
determining a second core ID corresponding to a second core that executes the first thread after the first thread is scheduled-in;
comparing the first and second core IDs;
updating a second cache register ID associated with a cache register of the second core when the first and second core IDs are different to replace the second cache register ID with the first cache register ID;
initiating the at least one stash transaction that corresponds to a first data frame received from the first I/O device;
broadcasting the at least one stash transaction to the plurality of cores; and
storing the first data frame in the cache register of the second core.
19. The method of claim 18 , further comprising updating the IOMMU mapping table corresponding to the first I/O device when the first and second core IDs are different to replace the first stash transaction destination ID with a second stash transaction destination ID, wherein the second stash transaction destination ID includes the second cache register ID associated with a cache register of the second core.
20. The method of claim 19 , further comprising updating the LIODN of the first I/O device when the first and second core IDs are different to replace the LIODN of the first I/O device with a LIODN of a second I/O device.