Programming a split gate bit cell
View Patent ↗A method of programming a split gate memory applies voltages differently to the terminals of the selected cells and the deselected cells. For cells being programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, programming is achieved by coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage. For cells not being programmed by not being coupled to a selected row, non-programming is maintained by coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected but sufficiently low to prevent programming.
1. In a split gate memory having a first sector of split gate memory cells arranged in rows and columns, wherein each split gate memory cell has a control gate, a select gate coupled to a word line along one of the rows, a drain terminal coupled to a bit line along one of the columns, and a source terminal, a method of selective programming, comprising:
for a split gate memory cell selected for programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage, coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage; and
for split gate memory cells split gate cells not being programmed by being coupled to a deselected row, coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied to the select gate during a read in which the split gate memory cells are deselected.
2. The method of claim 1 , further comprising:
for split gate memory cells not being programmed by being coupled to a deselected column and a selected word line, coupling the control gate to the first voltage, coupling the select gate to the second voltage, coupling the drain terminal to a fifth voltage greater than the fourth voltage, and coupling the source terminal to the third voltage.
3. The method of claim 2 , further comprising:
for the split gate memory cells not being programmed by being coupled to a deselected row and further characterized as being coupled to a deselected column, coupling the drain terminal to the fifth voltage.
4. The method of claim 3 , further comprising;
for the split gate memory cells not being programmed by being coupled to a deselected row further characterized as being coupled to a selected column, coupling the drain terminal to the current sink.
5. The method of claim 4 , wherein the split gate memory further comprises a second sector adjacent to the first sector arranged in rows and columns, wherein each split gate memory cell of the second sector has a control gate, a select gate coupled to a word line along one of the rows, a drain terminal coupled to one of the bit lines extending from the first sector and along the columns, and a source terminal, further comprising:
for a split gate memory cell of the second sector that is deselected by the second sector being deselected and the column is selected, coupling the control gate to a sixth voltage, coupling the select gate to the fourth voltage, coupling the drain terminal to the current sink, and coupling the source terminal to the fourth voltage.
6. The method of claim 5 , further comprising:
for a split gate memory cell of the second sector that is deselected by the second sector being deselected and the column being deselected, coupling the control gate to a sixth voltage, coupling the select gate to the fourth voltage, coupling the drain terminal to the sixth voltage, and coupling the source terminal to the fourth voltage.
7. The method of claim 1 , wherein the coupling the select gate to a fourth voltage for when the split gate memory cells are not being programmed is further characterized by the split gate memory cells having a threshold voltage and the fourth voltage being less than the threshold voltage above a voltage on the drain terminal.
8. The method of claim 1 , wherein the coupling the select gate to a fourth voltage for when the split gate memory cells are not being programmed is further characterized by the fourth voltage being greater than ground.
9. The method of claim 8 , wherein the first voltage is greater than the second voltage and the third voltage, the second voltage is greater than the fourth voltage, and the third voltage is greater than the second voltage.
10. The method of claim 1 , wherein the drain terminal of each split gate memory cell functions as a drain when being read and a source when being programmed and the source terminal functions as a source when being a read and a drain when being programmed.
11. A split gate memory, comprising:
a first sector of split gate memory cells arranged in rows and columns, wherein each split gate memory cell has a control gate, a select gate coupled to a word line along one of the rows, a drain terminal coupled to a bit line along one of the columns, and a source terminal; and
programming circuitry for programming by which:
for a split gate memory cell selected for programming by being coupled to a selected row and a selected column, coupling the control gate to a first voltage, coupling the select gate to a second voltage; coupling the drain terminal to a current sink that causes the split gate memory cell to be conductive, and coupling the source terminal to a third voltage, and
for split gate memory cells not being programmed by being coupled to a deselected row, coupling the control gate to the first voltage, coupling the select gate to a fourth voltage which is greater than a voltage applied, during a read, to the select gates of the split gate memory cells that are deselected.
12. The split gate memory of claim 11 , wherein the programming circuitry is further characterized by coupling a fifth voltage to the drain terminals of split gate memory cells that are deselected by being coupled to a deselected column, wherein the fourth voltage is less than the fifth voltage.
13. The split gate memory of claim 11 , wherein the programming circuitry is further characterized by the current sink inducing a sink voltage on the source terminals to which the current sink is coupled, wherein the sink voltage is greater than the fourth voltage.
14. The split gate memory of claim 11 , wherein the programming circuitry is further characterized by the voltage applied, during a read, to the select gates of the split gate memory cells that are deselected being ground.
15. The split gate memory of claim 11 further comprising:
a second sector of split gate memory cells arranged in rows and columns, wherein each split gate memory cell has a control gate, a select gate coupled to a word line along one of the rows, a drain terminal coupled to a bit line along one of the columns, and a source terminal; and
the programming circuitry is further characterized by coupling the fourth voltage to the select gates of the split gate memory cells of the second sector when the second sector is deselected during programming of the first sector of split gate memory cells.
16. A method for selectively programming a split gate memory, comprising:
providing a first sector of split gate memory cells arranged in rows and columns, wherein each split gate memory cell has a control gate, a select gate coupled to a word line along one of the rows, a drain terminal coupled to a bit line along one of the columns, and a source terminal;
selecting a column and a row to identify a selected split gate memory cell to be programmed and to identify deselected split gate memory cells not on both a selected row and selected column,
to the selected split gate memory cell, coupling a first voltage to the control gate, coupling a second voltage to the select gate, coupling a current sink to the drain terminal, and coupling a third voltage to the source terminal; and
to each of the deselected split gate memory cells not on a selected row, coupling a fourth voltage to the select gate, wherein the fourth voltage is greater than ground and less than the second voltage.
17. The method of claim 16 , further comprising, to each of the split gate memory cells not on a selected row and not on a selected column, coupling a fifth voltage to the drain terminal, wherein the fifth voltage is greater than the fourth voltage.
18. The method of claim 16 , further comprising, to each of the split gate memory cells not on a selected row but on a selected column, coupling the current sink to the drain terminal.
19. The method of claim 18 , wherein the current sink causes sink voltage on the drain terminals to which the current sink is coupled, wherein the sink voltage is greater than the fourth voltage.
20. The method of claim 16 , wherein the coupling the fourth voltage to the select gate is further characterized by being less than the third voltage whereby the source terminal functions as a drain and the drain terminal functions as a source during programming.