Flash memory with bias voltage for word line/row driver
View Patent ↗A memory device includes a word line driver circuit, a write voltage generator for providing a write voltage to the word line driver during a write operation to memory cells coupled to the word line driver circuit, and a write bias generator including an output node for providing a write bias voltage that is different from the write voltage to the word line driver circuit during a write operation to memory cells coupled to the word line driver circuit. The write bias voltage is used to reduce current drawn by the word line driver circuit from the write voltage generator during a write operation to memory cells coupled to the word line driver circuit.
1. A memory comprising:
a word line driver circuit;
a write voltage generator for providing a write voltage to the word line driver during a write operation to memory cells coupled to the word line driver circuit;
a write bias generator including an output node for providing a write bias voltage that is different from the write voltage to the word line driver circuit during a write operation to memory cells coupled to the word line driver circuit, wherein the write bias voltage is used to reduce current drawn by the word line driver circuit from the write voltage generator during a write operation to memory cells coupled to the word line driver circuit, wherein the write bias generator includes:
a diode configured transistor including a first current terminal for receiving the write voltage and a second current terminal connected to the output node;
a first transistor having a first current terminal connected to the output node, a second current terminal, and a control terminal;
a second transistor having a first current terminal for receiving the write voltage, a second current terminal connected to the control terminal of the first transistor, and a control terminal connected to the output node, wherein during a write mode, the conductivity of the second transistor controls the conductivity of the first transistor for regulating the voltage of the output node.
2. The memory of claim 1 wherein the write bias generator further comprises a current source, wherein during a write mode, the conductivity of the first transistor is controlled to control the amount of current flowing through the first transistor between the output node and the current source.
3. The memory of claim 2 further comprising a second current source located in parallel with the current source, wherein during a read recovery mode, the second current source provides current to the second current terminal of the diode connected transistor in parallel with the first current source, wherein during a write mode, the second current source is not utilized.
4. The memory of claim 2 further comprising a second current source, the second current source providing current to the second current terminal of the second transistor during a write mode.
5. The memory of claim 4 wherein the second current source is not utilized in providing a voltage at the output node during a write mode.
6. The memory of claim 1 wherein the write bias generator further includes a second diode configured transistor located in parallel with the first diode configured transistor, wherein the second diode configured transistor includes a first current terminal for receiving the write voltage during a write operation and a second current terminal connected to the output node.
7. The memory of claim 6 wherein the second diode configured transistor is not utilized in providing a voltage at the output node during a read recovery mode.
8. The memory of claim 1 wherein during a read recovery mode, the second transistor is not utilized in controlling the voltage of the output node.
9. The memory of claim 1 further comprising a read bias generator, the read bias generator including a second diode configured transistor having a first current terminal for receiving a read voltage and a second current terminal configured to provide a read bias voltage, wherein the diode configured transistor is approximately the same size as the second diode configured transistor.
10. The memory of claim 1 further comprising:
a read bias generator, the read bias generator including a second diode configured transistor having a first current terminal for receiving a read voltage and a second current terminal configured to provide a read bias voltage;
the write bias generator further comprises a first current source, wherein during a write mode, the conductivity of the first transistor is controlled to control the amount of current flowing through the first transistor between the output node and the first current source;
the read bias generator further comprises a second current source coupled to the second current terminal of the second diode configured transistor;
wherein the first current source is sized to provide less current than the second current source.
11. The memory of claim 10 further comprising a third current source located in parallel with the first current source, wherein during a read recovery mode, the third current source provides current to second current terminal of the diode connected transistor in parallel with the first current source, wherein during a write mode, the third current source is not utilized.
12. The memory of claim 11 wherein the first current source and the third current source are sized together to provide approximately the same amount of current as the second current source.
13. The memory of claim 1 further comprising:
a read bias generator, the read bias generator including an output node for providing a read bias voltage;
a selection circuit having a first input coupled to the output node of the write bias generator and a second input coupled to the output node of the read bias generator, the selection circuit having an output coupled to a control terminal of the word line driver circuit, the control terminal is used to reduce current drawn by the word line driver circuit during an operation to memory cells coupled to the word line driver circuit.
14. The memory of claim 13 further comprising:
a read voltage generator to provide a read voltage;
a second selection circuit having a first input coupled to the write voltage generator and a second input coupled to the read voltage generator, wherein the output of the second selector circuit provides a voltage for biasing a word line connected to the output of the word line driver circuit during a memory operation of the memory.
15. The circuit of claim 13 wherein during a write to memory cells coupled to the word line driver circuit, the output node of the write bias generator provides the write bias voltage and the selection circuit couples its first input to its output, after the write operation, the write bias generator enters a read recovery mode where the voltage of the write bias voltage is moved to a voltage approximately equal to a voltage of the output node of the read bias generator, after the voltage of the output node of the write bias generator approximately equals the voltage of the output node of the read bias generator, the selection circuit couples its second input to its output.
16. The memory of claim 1 wherein the write voltage generator is a positive voltage node and the output of the write bias generator provides a positive write bias voltage during a write operation, the memory further comprising:
a negative write voltage generator;
a negative a write bias generator including an output node for providing a negative write bias voltage that is different from the negative write voltage to the word line driver circuit during a write operation to memory cells coupled to the word line driver circuit, wherein the negative write bias voltage is used to reduce current drawn by the word line driver circuit from the negative write voltage generator during a write operation to memory cells coupled to the word line driver circuit.
17. The memory of claim 16 wherein the negative write bias generator includes:
a second diode configured transistor including a first current terminal for receiving the negative write voltage and a second current terminal connected to the output node of the negative write bias generator;
a third transistor having a first current terminal connected to the output node of the negative write bias circuit, a second current terminal, and a control terminal;
a fourth transistor having a first current terminal for receiving the negative write voltage, a second current terminal connected to the control terminal of the third transistor, and a control terminal connected to the output node of the negative write bias circuit, wherein during a write mode, the conductivity of the fourth transistor controls the conductivity of the third transistor for regulating the voltage of the output node of the negative write bias generator.
18. The memory of claim 1 further comprising:
a plurality of word line driver circuits, for each word line driver circuit of the plurality, the write voltage generator provides a write voltage to a word line driver circuit of the plurality during a write operation to memory cells coupled to the word line driver circuit of the plurality;
wherein for each word line driver circuit of the plurality, the output node provides a write bias voltage to a word line driver circuit of the plurality during a write operation to memory cells coupled to the word line driver circuit of the plurality, wherein the write bias voltage is used to reduce current drawn by the word line driver circuit of the plurality from the write voltage generator during a write operation to memory cells coupled to the word line driver circuit of the plurality.
19. A method of operating a word line driver comprising:
performing a write operation to memory cells coupled to a word line driver, the performing a write operation includes:
providing a write voltage to the word line driver from an output of a write voltage generator;
providing a write bias voltage to the word line driver from an output of a write bias generator, wherein the word line driver uses the write bias voltage to reduce current drawn by the word line driver circuit from the write voltage generator output during the write operation to the memory cells coupled to the word line driver circuit, wherein the providing the write bias voltage includes the write bias generator receiving the write voltage from the output of the write voltage generator and using a first transistor and second transistor in generating the write bias voltage from the write voltage;
operating in a read recovery mode following the write operation, the operating in a read recovery mode includes:
receiving, by the write bias generator, a voltage from the output of the write voltage generator;
using, by the write bias generator, the voltage provided by the output of the write voltage generator to generate a bias voltage at the output of the write bias generator without the use of the first transistor and the second transistor.
20. The method claim 19 wherein the operating in the read recovery mode includes:
initially providing the voltage of the output of the write bias generator to a terminal of the word line driver;
matching the voltage of the output to the write bias generator to a voltage of an output of a read bias generator;
matching the voltage of the output of the write voltage generator to a voltage of an output of a read voltage generator;
after the matching and the matching, providing the voltage of the output of the read bias generator to the terminal of the word line driver.
21. The method of claim 19 wherein:
the first transistor has a first current terminal connected to the output of the write bias generator;
the using a first transistor and second transistor in generating the write bias voltage from the write voltage includes:
receiving, by a first current terminal of a second transistor, the write voltage, a second current terminal of the second transistor is connected to a control terminal of the first transistor and a control terminal of the second transistor is connected to the output of the write bias generator,
regulating the voltage of the output of the write bias generator, wherein the regulating includes the conductivity of the second transistor controlling the conductivity of the first transistor.