Methods relating to the fabrication of devices having conductive substrate vias with catch-pad etch-stops
View Patent ↗An electronic device having a conductive substrate via extending between a conductor on a rear face and a conductor over a front face of the substrate includes a multi-layered etch-stop beneath the front surface conductor. The etch-stop permits use of a single etchant to penetrate both the substrate and any overlying semiconductor and/or dielectric without attacking the overlying front surface conductor. This is especially important when the semiconductor and dielectric are so thin as to preclude changing etchants when these regions are reached during etching. The etch-stop is preferably a stack of N≧2 pairs of sub-layers, where a first sub-layer comprises stress relieving and/or adhesion promoting material (e.g., Ti), and the second sub-layer comprises etch resistant material (e.g., Ni). In a further embodiment, where the device includes field effect transistors having feedback sensitive control gates, the etch-stop material is advantageously used to form gate shields.
1. A method, comprising:
providing a substrate having a front surface;
forming above the front surface an electrically conductive multi-layered etch-stop region adapted to resist etchants that etch the substrate;
forming above the front surface a front surface conductor in electrical contact with the multi-layered etch-stop region;
etching a through-substrate via passage in the substrate, extending from a rear surface of the substrate through the substrate to the multi-layered etch-stop region; and
forming an electrical conductor in the through-substrate via passage extending substantially from the rear surface of the substrate to the multi-layered etch-stop region and making electrical contact to the front surface conductor via the multi-layered etch-stop region, thereby forming a conductive through-substrate via.
2. The method of claim 1 wherein the step of etching the through-substrate via passage comprises etching the substrate using a plasma containing fluorine.
3. The method of claim 1 wherein the etching step further comprises:
mounting on a carrier an initial substrate from which the substrate can be formed so that an initial rear face of the initial substrate is exposed;
removing material from the initial rear face thereby thinning the initial substrate so as to provide the substrate having a newly exposed rear face from which the etching step can proceed;
providing an etch resistant mask on the newly exposed rear face having a closed portion and an open portion, the open portion substantially defining a location of the through-substrate via passage; and
etching the substrate through the open portion to form the through-substrate via passage.
4. The method of claim 3 further comprising, after the etching step, removing the etch resistant mask.
5. The method of claim 1 wherein the step of forming an electrically conductive multi-layered etch-stop region comprises:
forming a stack of N≧2 pairs of electrically conductive sub-layers in either order, wherein a first of the electrically conductive sub-layers is chosen from materials having stress relief or adhesion promoting properties or both, and a second of the electrically conductive sub-layers is chosen from materials adapted to resist the etching step.
6. The method of claim 5 wherein the first of the conductive sub-layers comprises at least one of the group consisting of titanium, chromium, tantalum, and combinations thereof, and the second of the conductive sub-layers comprises at least one of the group consisting of nickel, aluminum, indium-tin oxide, and combinations thereof.
7. The method of claim 1 further comprising:
forming over the front surface a field effect transistor having a gate; and
forming a gate shield overlying the gate.
8. The method of claim 7 wherein the gate shield and the electrically conductive multi-layered etch-stop region are formed from the same material.
9. The method of claim 7 wherein the gate shield and the electrically conductive multi-layered etch-stop region are formed by depositing and patterning a common conductor layer.
10. The method of claim 1 wherein at least a portion of the multi-layered etch-stop region is formed within the front surface conductor.
11. A method, comprising:
providing a substrate having a first surface and a second surface;
etching a through-substrate via passage in the substrate utilizing a first etchant, the through-substrate via passage extending from the first surface to the second surface;
depositing an electrical conductor in the through-substrate via passage to produce conductive through-substrate via.
forming a front surface conductor above the second surface;
forming a multi-layered etch-stop region electrically coupled to the front surface conductor, the multi-layered etch-stop region comprising a material resistant to the first etchant utilized to etch the substrate, the multi-layered etch-stop region including at least one layer pair comprising:
a first sub-layer of a stress relief or adhesion promoting material; and
a second sub-layer of an etch resistant material formed in contact with the fist sub-layer of stress relief or adhesion promoting material.
12. A method, comprising:
providing a substrate having an upper surface and a lower surface, a semiconductor layer formed over the upper surface of the substrate, and a dielectric layer formed over the semiconductor layer;
forming a catch-pad conductor over the dielectric layer;
forming a multi-layered etch-stop region over the dielectric layer and electrically coupled to the catch-pad conductor; and
forming a through-substrate via extending from the lower surface of the substrate, through the semiconductor layer, through the dielectric layer, and to the multi-layered etch stop region, the through-substrate via electrically coupled to the catch-pad conductor through the multi-layered etch stop region.
13. The method of claim 12 wherein forming a through-substrate via comprises:
etching a through-substrate via passage in the substrate utilizing a first etchant, the through-substrate via passage extending from the lower surface, through the substrate, to the multi-layered etch-stop region; and
depositing an electrical conductor in the through-substrate via passage to form the conductive through-substrate via.
14. The method of claim 13 wherein the multi-layered etch-stop region comprises multiple layers of an etch resistant material having lower etch rate than does the substrate when exposed to the first etchant.
15. The method of claim 14 wherein the semiconductor layer comprises gallium nitride, wherein the dielectric layer comprises silicon nitride, and wherein the etch resistant material is selected form the group consisting of nickel, aluminum, indium-tin oxide, and combinations thereof.
16. The method of claim 12 wherein the multi-layered etch-stop region comprises multiple layers of a stress relief or adhesion promoting material.
17. The method of claim 16 wherein the semiconductor layer comprises gallium nitride, wherein the dielectric layer comprises silicon nitride, and wherein the stress relief or adhesion promoting material is selected from the group consisting of titanium, chromium, tantalum, and combinations thereof.
18. The method of claim 12 wherein the multi-layered etch-stop region comprises:
at least two etch resistant layers; and
at least one layer of a stress relief or adhesion promoting material interspersed with the at least two etch resistant layers.
19. The method of claim 12 wherein the multi-layered etch-stop region comprises:
at least one layer pair comprising a first layer of an etch resistant material and a second layer of a stress relief or adhesion promoting material; and
a capping layer formed over the at least one layer pair.
20. The method of claim 12 wherein the catch-pad conductor has a width greater than the width of the through-substrate via, as taken along the upper surface of the substrate.