IP Library Patent Application 13777715
Patent Application
App. No. 13/777,715

Method for Bonding Semiconductor Devices

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
13/777,715
Abstract

A method of attaching first and second semiconductor devices to one another includes applying plating gel over a surface of a first semiconductor device, positioning bonding regions of a second semiconductor device in contact with the plating gel on corresponding bonding regions on the first semiconductor device, and reacting at least some the plating gel to bond the second semiconductor device to the first semiconductor device.

Claims (31)

1 . A method comprising:

applying electroless plating gel over a surface of a first semiconductor device;

positioning bonding regions of a second semiconductor device in contact with the plating gel on corresponding bonding regions on the first semiconductor device; and

reacting at least some of the electroless plating gel to bond the second semiconductor device to the first semiconductor device.

2 . The method of claim 1 wherein the reacting the electroless plating gel includes applying a thermal treatment.

3 . The method of claim 1 wherein the reacting the electroless plating gel includes applying a photochemical treatment.

4 . The method of claim 1 wherein the first semiconductor device is one of the group consisting of an integrated circuit die and an integrated circuit wafer.

5 . The method of claim 1 wherein the second semiconductor device is one of the group consisting of an integrated circuit die and an integrated circuit wafer.

6 . The method of claim 1 wherein the electroless plating gel includes copper.

7 . The method of claim 1 wherein the bonding regions include at least one of a group consisting of: bond pads, through-silicon vias, recessed bond pads, and pillars.

8 . The method of claim 1 wherein the bonding regions are accessed through an opening in a passivation material on the surface of the first semiconductor device.

9 . The method of claim 8 further comprising removing unreacted electroless plating gel.

10 . A method comprising:

applying an electroless plating gel to bonding regions on a first semiconductor device;

aligning each of a plurality of bonding regions on a second semiconductor device in contact with the electroless plating gel on a respective one of the bonding regions on the first semiconductor device; and

forming a bond between the bonding regions on the first and second semiconductor devices by converting metallic ions in the electroless plating gel to metal.

11 . The method of claim 10 wherein the forming the bond comprises at least one of group consisting of: applying a thermal treatment and applying a photochemical treatment.

12 . The method of claim 10 wherein the first semiconductor device is one of the group consisting of an integrated circuit die and an integrated circuit wafer and the second semiconductor device is one of the group consisting of an integrated circuit die and an integrated circuit wafer.

13 . The method of claim 10 wherein the bonding regions include at least one of a group consisting of: bond pads, through-silicon vias, recessed bond pads, and pillars.

14 . The method of claim 10 wherein the bonding regions are accessed through an opening in a passivation material on a surface of the first semiconductor device.

15 . The method of claim 10 wherein the electroless plating gel includes copper, a reducing agent, and a complexing agent.

16 . A method comprising:

depositing a plating gel on a bonding region of a first semiconductor device;

orienting a bonding region of a second semiconductor device in contact with the plating gel on the bonding region of the first semiconductor device; and

inducing a reaction in the plating gel to form a metal bond between the bonding regions of the first and second semiconductor devices.

17 . The method of claim 16 wherein:

depositing the plating gel includes stencil printing over a surface of the first semiconductor device.

18 . The method of claim 16 further comprising:

removing unreacted plating gel.

19 . The method of claim 16 wherein the bonding region includes at least one of a group consisting of: a bond pad, a through-silicon via, a recessed bond pads, and a pillar.

20 . The method of claim 16 wherein the inducing the reaction comprises at least one of group consisting of: applying a thermal treatment and applying a photochemical treatment.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 030445/0737 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030445/0709 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030445/0581 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2013
From: MATHEW, VARUGHESE
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029882/0611 →