Robust sector ID scheme for tracking dead sectors to automate search and copydown
View Patent ↗A brownout tolerant EEPROM emulator ( 18 ) manages memory operations at a volatile memory ( 20 ) and non-volatile memory ( 24 ) using a plurality of sector status bits ( 451 ) and forward/reverse skip flags ( 452, 453 ) stored in a sector identification record ( 45 ) of each sector to define a plurality of status indicators arranged sequentially to specify a plurality of sector configuration states for each memory sector, and to automatically bypass one or more dead sectors in the non-volatile memory array during forward copydown and reverse search operations.
1. An emulated EEPROM system comprising:
a volatile random access memory for storing and accessing data via one or more access requests;
a non-volatile memory comprising a plurality of sectors for storing records of the data stored in the volatile random access memory, each sector of the plurality of sectors comprising a corresponding sector header for storing a plurality of sector status bits defining a plurality of status indicators arranged to sequentially specify a lifecycle sequence of sector configuration states for said sector, where each sector header further comprises a sector skip indicator location for one or more adjacent dead sectors in the non-volatile memory for storing a sector skip indicator which may be used to automatically bypass the one or more adjacent dead sectors during automated search or copydown operations; and
a control module coupled to the non-volatile memory and the volatile memory, where the control module is operable to program the plurality of sector status bits in the sector header of each sector with first and second program operations to change a sector configuration state for the sector, where the control module comprises an address generation unit for generating a controlled address sequence based on a sector size adjustment signal derived from the sector skip indicator in the sector header.
2. The emulated EEPROM system of claim 1 , where the non-volatile memory comprises a flash memory for storing a plurality of flash memory sectors, each of which includes one or more EEPROM data records and a corresponding sector header record.
3. The emulated EEPROM system of claim 2 , where flash memory comprises a NAND flash array or a NOR flash array.
4. The emulated EEPROM system of claim 1 , wherein the plurality of sector status bits comprises:
a first plurality of status bits for programming a first status indicator upon performing a first program operation, and
a second plurality of status bits for programming a second status indicator upon performing a second program operation,
where the second plurality of status bits are stored adjacent to the first plurality of status bits and in more significant bit positions in the plurality of sector status bits.
5. The emulated EEPROM system of claim 1 , where each sector header further comprises a forward skip indicator location for one or more adjacent dead sectors in the non-volatile memory for storing a forward skip indicator which may be used to automatically bypass the one or more adjacent dead sectors during a forward copydown sequence.
6. The emulated EEPROM system of claim 1 , where each sector header further comprises a reverse skip indicator location for one or more adjacent dead sectors in the non-volatile memory for storing a reverse skip indicator which may be used to automatically bypass the one or more adjacent dead sectors during a reverse search sequence.
7. An emulated electrically erasable programmable read-only memory (EEEPROM) device, comprising:
an emulation memory having a plurality of sectors for sequentially storing information in a plurality of records, each sector comprising:
a sector identification record location for storing a plurality of sector status bits defining a plurality of status indicators arranged to sequentially specify a lifecycle sequence of sector configuration states for said sector,
a forward skip indicator location for one or more adjacent dead sectors in the emulation memory which may be used to automatically bypass the one or more adjacent dead sectors during a forward copydown sequence, and
a reverse skip indicator location for one or more adjacent dead sectors in the emulation memory which may be used to automatically bypass the one or more adjacent dead sectors during a reverse search sequence; and
a memory controller coupled to the emulation memory, where the memory controller is operable to program the plurality of sector status bits in the sector identification record of each sector with first and second program operations to change a sector configuration state for the sector.
8. The EEEPROM device of claim 7 , where the emulation memory comprises a flash memory for storing a plurality of flash memory sectors, each of which includes one or more EEPROM data records and a corresponding sector identification record.
9. The EEEPROM device of claim 7 , where the memory controller comprises an address generation unit for generating a controlled address sequence based on a sector size adjustment signal derived from a forward skip indicator stored in the forward skip indicator location.
10. The EEEPROM device of claim 7 , where the memory controller comprises an address generation unit for generating a controlled address sequence based on a sector size adjustment signal derived from a reverse skip indicator stored in the reverse skip indicator location.