Integration technique using thermal oxide select gate dielectric for select gate and replacement gate for logic
View Patent ↗A control gate overlying a charge storage layer is formed. A thermally-grown oxygen-containing layer is formed over the control gate. A polysilicon layer is formed over the oxygen-containing layer and planarized. A first masking layer is formed defining a select gate location laterally adjacent the control gate and a second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening in the dielectric. A high-k gate dielectric and logic gate are formed in the opening.
1. A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising:
forming a control gate overlying a charge storage layer over the substrate in the NVM region;
forming a thermally-grown oxygen-containing dielectric layer over the substrate and the control gate in the NVM region and over the substrate in the logic region;
forming a polysilicon layer over the thermally-grown oxygen-containing dielectric layer in the NVM region and the logic region;
planarizing the polysilicon layer;
forming a first masking layer in the NVM region wherein the first masking layer defines a select gate location laterally adjacent the control gate in the NVM region;
forming a second masking layer in the logic region wherein the second masking layer defines a logic gate location in the logic region;
using the first masking layer to remove exposed portions of the polysilicon layer from the NVM region, wherein a first portion of the polysilicon layer remains at the select gate location to form a select gate;
using the second masking layer to remove exposed portions of the polysilicon layer from the logic region, wherein a second portion of the polysilicon layer remains at the logic gate location;
forming a dielectric layer in the NVM region and the logic region, wherein the dielectric layer is formed over the select gate, the control gate, and the second portion of the polysilicon layer;
planarizing the dielectric layer to expose the second portion of the polysilicon layer;
removing the second portion of the polysilicon layer and a portion of the thermally-grown oxygen-containing dielectric layer to result in an opening at the logic gate location which exposes the substrate; and
forming a high-k gate dielectric layer and a logic gate within the opening in the logic region.
2. The method of claim 1 , wherein the step of forming the first masking layer is performed such that:
the first masking layer is directly over the control gate, and
a first edge of the first masking layer extends laterally from the control gate onto the polysilicon layer to define the select gate location laterally adjacent the control gate in the NVM region.
3. The method of claim 1 , wherein the first masking layer and the second masking layer are portions of a same patterned masking layer, and wherein the steps of using the first masking layer to remove exposed portions of the polysilicon layer from the NVM region and using the second masking layer to remove exposed portions of the polysilicon layer from the logic region are performed simultaneously.
4. The method of claim 1 , further comprising:
prior to the step of forming the thermally-grown oxygen-containing dielectric layer, forming an oxide spacer on a sidewall of the control gate.
5. The method of claim 4 , wherein a thickness of the oxide spacer is in a range of 60 to 150 Angstroms.
6. The method of claim 1 , wherein prior to the step of removing the second portion of the polysilicon layer and the portion of the thermally-grown oxygen-containing dielectric layer to result in the opening at the logic gate location, the method further comprises:
forming a protection layer over the select gate and the control gate in the NVM region and over the second portion of the polysilicon layer in the logic region; and
patterning the protection layer to remove portions of the protection layer from the logic region.
7. The method of claim 6 , wherein the step of forming the high-k gate dielectric and the logic gate comprises:
forming the high-k gate dielectric layer over the protection layer in the NVM region and over the dielectric layer and within the opening in the logic region;
forming a gate layer over the high-k gate dielectric layer and the protection layer in the NVM region and over the high-k gate dielectric layer and within the opening in the logic region; and
planarizing the gate layer such that the gate layer, the protection layer, and the high-k gate dielectric are removed from the NVM region.
8. The method of claim 1 , wherein top surfaces of the logic gate and the select gate are substantially coplanar.
9. The method of claim 1 , wherein after the steps of using the first and second masking layers to remove exposed portions of the polysilicon layer in the NVM region and the logic region, the method further comprises:
forming a first source/drain region in the substrate laterally adjacent the select gate and a second source/drain region in the substrate laterally adjacent the control gate, such that the select gate and the control gate are located between the first and second source/drain regions; and
forming a third source/drain region in the substrate laterally adjacent a first sidewall of the second portion of the polysilicon layer and a fourth source/drain region in the substrate laterally adjacent a second sidewall of the second portion of the polysilicon layer.
10. The method of claim 9 , wherein after the steps of using the first and second masking layers to remove exposed portions of the polysilicon layer in the NVM region and the logic region, the method further comprises:
forming a first sidewall spacer surrounding outer sidewalls of the select gate and the control gate and a second sidewall spacer surrounding the second portion of the polysilicon layer.
11. The method of claim 1 , wherein the step of forming the control gate overlying the charge storage layer over the substrate in the NVM region comprises:
forming the charge storage layer over the substrate in the NVM region and the logic region;
forming a second polysilicon layer over the charge storage layer in the NVM region and the logic region; and
patterning the second polysilicon layer and the charge storage layer to form the control gate in the NVM region and to remove the second polysilicon layer and the charge storage layer from the logic region.
12. The method of claim 1 , wherein the charge storage layer comprises at least one of nanocrystals or a nitride.
13. The method of claim 12 , wherein the control gate comprises polysilicon.
14. The method of claim 1 , wherein the logic gate comprises a metal.
15. A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising:
forming a control gate overlying a charge storage layer over the substrate in the NVM region, wherein the control gate comprises polysilicon;
forming an oxide spacer on a sidewall of the control gate;
thermally growing an oxygen-containing layer on the substrate and on the control gate;
forming a polysilicon layer over the oxygen-containing layer in the NVM region and the logic region;
planarizing the polysilicon layer;
forming a patterned masking layer in the NVM region and the logic region, wherein the patterned masking layer comprises a first masking portion formed over the polysilicon layer and control gate in the NVM region and a second masking portion over the polysilicon layer in the logic region, wherein:
the first masking portion is directly over the control gate and a first edge of the first masking portion extends laterally from the control gate onto the polysilicon layer to define a select gate location laterally adjacent the control gate in the NVM region; and
the second masking portion defines a logic gate location in the logic region;
using the patterned masking layer to remove exposed portions of the polysilicon layer, wherein a first portion of the polysilicon layer remains at the select gate location to form a select gate and a second portion of the polysilicon layer remains at the logic gate location;
forming a dielectric layer in the NVM region and the logic region, wherein the dielectric layer is formed over the select gate, the control gate, and the second portion of the polysilicon layer;
planarizing the dielectric layer to expose the second portion of the polysilicon layer;
forming a protection layer over the select gate and the control gate in the NVM region, wherein the protection layer exposes the logic region;
removing the second portion of the polysilicon layer and a portion of the oxygen-containing layer to result in an opening at the logic gate location;
forming a high-k gate dielectric layer over the protection layer in the NVM region and over the dielectric layer and within the opening in the logic region; and
forming a logic gate in the logic region within the opening and over the high-k gate dielectric layer.
16. The method of claim 15 , wherein a thickness of the oxide spacer is in a range of 60 to 150 Angstroms.
17. The method of claim 15 , wherein the step of forming the logic gate comprises:
forming a gate layer over the high-k gate dielectric layer and the protection layer in the NVM region and over the high-k gate dielectric layer and within the opening in the logic region; and
planarizing the gate layer such that the gate layer, the protection layer, and the high-k gate dielectric layer are removed from the NVM region.
18. The method of claim 15 , wherein after the step of using the patterned masking layer to remove exposed portions of the polysilicon layer and prior to the step of forming the protection layer, the method further comprises:
forming a first source/drain region in the substrate laterally adjacent the select gate and a second source/drain region in the substrate laterally adjacent the control gate, such that the select gate and the control gate are located between the first and second source/drain regions;
forming a third source/drain region in the substrate laterally adjacent a first sidewall of the second portion of the polysilicon layer and a fourth source/drain region in the substrate laterally adjacent a second sidewall of the second portion of the polysilicon layer; and
forming a first sidewall spacer surrounding outer sidewalls of the select gate and the control gate and a second sidewall spacer surrounding the second portion of the polysilicon layer.
19. A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising:
forming a nanocrystal stack layer over the substrate in the NVM region and the logic region;
forming a first polysilicon layer over the nanocrystal stack layer in the NVM region and the logic region;
patterning the first polysilicon layer and the nanocrystal stack layer to form a control gate in the NVM region and to remove the first polysilicon layer and the charge storage layer from the logic region;
forming a thermally-grown oxygen-containing dielectric layer over the substrate and the control gate in the NVM region and over the substrate in the logic region; forming a second polysilicon layer over the oxygen-containing dielectric layer in the NVM region and the logic region;
planarizing the second polysilicon layer, wherein the oxygen-containing dielectric layer comprises a sidewall portion located along the sidewall of the control gate;
forming a patterned masking layer in the NVM region and the logic region, wherein the patterned masking layer comprises a first masking portion formed over the second polysilicon layer and the control gate in the NVM region and a second masking portion over the second polysilicon layer in the logic region, wherein:
the first masking portion is directly over the control gate and a first edge of the first masking portion extends laterally from the control gate onto the second polysilicon layer to define a select gate location laterally adjacent the control gate in the NVM region; and
the second masking portion defines a logic gate location in the logic region;
using the patterned masking layer to remove exposed portions of the second polysilicon layer, wherein a first portion of the second polysilicon layer remains at the select gate location to form a select gate and a second portion of the second polysilicon layer remains at the logic gate location;
forming a dielectric layer in the NVM region and the logic region, wherein the dielectric layer is formed over the select gate, the control gate, and the second portion of the second polysilicon layer;
planarizing the dielectric layer to expose the second portion of the second polysilicon layer;
forming a protection layer over the select gate and the control gate in the NVM region and over the second polysilicon layer in the logic region;
patterning the protection layer to remove portions of the protection layer from the logic region;
removing the second portion of the second polysilicon layer and a portion of the thermally-grown oxygen-containing dielectric layer to result in an opening at the logic gate location;
forming a high-k gate dielectric layer over the protection layer in the NVM region and over the dielectric layer and within the opening in the logic region; and
forming a logic gate in the logic region within the opening and over the high-k gate dielectric layer.
20. The method of claim 19 , wherein the step of forming the logic gate comprises:
forming a gate layer over the high-k gate dielectric layer and the protection layer in the NVM region and over the high-k gate dielectric layer and within the opening in the logic region; and
planarizing the gate layer such that the gate layer, the protection layer, and the high-k gate dielectric layer are removed from the NVM region.