IP Library Granted Patent US 8,786,350
Granted Patent B1
US 8,786,350 · App. 13/740,823 · Granted Jul 22, 2014

Transmission system

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Quick Facts
Patent No.
US 8,786,350
App. No.
13/740,823
Granted
Jul 22, 2014
Kind
B1
Abstract

A signal transmission system ( 10 ) includes a signal generator circuit ( 12 ); a signal regenerator circuit ( 14 ) coupled to the signal generator circuit by conductive lines ( 16, 18 ). The signal regenerator circuit receives input signals from the signal generator circuit on the conductive lines, and the regenerator circuit includes cascoded transistors ( 39, 41 ) and level-shifting circuits ( 26 ) coupled to the cascoded transistors. The cascoded transistors amplify the input signals to provide amplified signals. The level-shifting circuits shift a voltage level of the amplified signals to provide level-shifted signals.

Claims (54)

1. A signal transmission system comprising:

a signal generator circuit;

a signal regenerator circuit coupled to the signal generator circuit by conductive lines with parasitic resistance and capacitance, wherein

the signal regenerator circuit receives input signals from the signal generator circuit on the conductive lines, and

the signal regenerator circuit includes cascoded transistors, level-shifting circuits coupled to the cascoded transistors, and a plurality of capacitors, wherein;

the cascoded transistors amplify the input signals to provide amplified signals;

the level-shifting circuits shift a voltage level of the amplified signals to provide level-shifted signals; and

each of the plurality of capacitors is coupled to a respective one of the conductive lines between the signal generator circuit and the cascoded transistors.

2. The system of claim 1 , further comprising:

a first supply voltage coupled to control operation of the cascoded transistors;

a charge pump coupled to the signal regenerator circuit to provide a second supply voltage to the signal regenerator circuit, wherein the second supply voltage is greater than the first supply voltage.

3. A signal transmission system comprising:

a signal generator circuit;

a signal regenerator circuit coupled to the signal generator circuit by conductive lines with parasitic resistance and capacitance, wherein

the signal regenerator circuit receives input signals from the signal generator circuit on the conductive lines, and

the signal regenerator circuit includes cascoded transistors, a headroom voltage circuit coupled to the cascoded transistors, and level-shifting circuits coupled to the cascoded transistors, wherein the cascoded transistors amplify the input signals to provide amplified signals and the level-shifting circuits shift a voltage level of the amplified signals to provide level-shifted signals.

4. The system of claim 3 , the signal regenerator circuit further comprising:

saturation limit circuitry coupled to the headroom voltage circuit.

5. The system of claim 2 , the signal regenerator circuit further comprising:

a headroom voltage circuit coupled between the charge pump and the cascoded transistors.

6. The system of claim 1 , wherein the cascoded transistors are lateral NPN bipolar transistors.

7. The system of claim 1 , wherein the signal regenerator circuit further includes a flip-flop circuit coupled to receive the level-shifted signals and provide an output signal from the signal regenerator circuit.

8. The system of claim 2 , wherein the level-shifting circuits comprise:

a first capacitor, an input to the first capacitor is coupled between a voltage headroom circuit and the cascoded transistors;

an N-channel transistor having a source coupled to a supply voltage and a gate and a drain coupled to an output of the first capacitor;

a P-channel transistor having a source coupled to a supply voltage and a gate and a drain coupled to the output of the first capacitor; and

an inverter having an input coupled to the output of the first capacitor and an output no greater than a voltage level of the first supply voltage.

9. The system of claim 1 , wherein the signal regenerator circuit further includes a bias circuit coupled the cascoded transistors.

10. A signal transmission system, comprising:

a pair of amplifying transistors;

a pair of transmission lines, wherein each of the transmission lines is coupled to provide input signals to a respective one of the amplifying transistors;

a pair of level-shifting circuits, each of the level-shifting circuits coupled to a respective one of the amplifying transistors, wherein the level-shifting circuits reduce voltage of amplified signals from the amplifying transistors; and

a voltage headroom circuit coupled to the pair of amplifying transistors.

11. The system of claim 10 , further comprising:

saturation limiting circuitry coupled to the voltage headroom circuit.

12. A signal transmission system, comprising:

a pair of amplifying transistors;

a pair of transmission lines, wherein each of the transmission lines is coupled to provide input signals to a respective one of the amplifying transistors;

a pair of level-shifting circuits, each of the level-shifting circuits coupled to a respective one of the amplifying transistors, wherein the level-shifting circuits reduce voltage of amplified signals from the amplifying transistors;

a pair of capacitors, wherein each of the capacitors is coupled between a respective one of the amplifying transistors and the level-shifting circuits; and

a pair of capacitors, wherein each of the capacitors is coupled between a respective one of the amplifying transistors and the level-shifting circuits.

13. The system of claim 10 , wherein the level-shifting circuits comprise:

an N-channel transistor having a source coupled to a supply voltage and a gate and a drain coupled to an output of a first capacitor;

a P-channel transistor having a source coupled to a supply voltage and a gate and a drain coupled to the output of the first capacitor; and

an inverter having an input coupled to the output of the first capacitor.

14. The system of claim 10 , further comprising:

a pair of capacitors, wherein each of the capacitors is coupled between a respective one of the amplifying transistors and the transmission lines.

15. The system of claim 10 , wherein the amplifying transistors are lateral bipolar transistors, the voltage headroom circuit includes first and second P-channel transistors with a gate of the first P-channel transistor coupled to a drain of the second P-channel transistor, and a gate of the second P-channel transistor coupled to a drain of the first P-channel transistor.

16. The system of claim 10 , further comprising:

a charge pump coupled to provide a first voltage to the voltage headroom circuit, wherein the first voltage is greater than a supply voltage provided to the amplifying transistors.

17. A method of repeating a transmitted signal comprising:

receiving a pair of differential signals from a driver circuit;

generating amplified signals by amplifying the differential signals using respective cascoded amplifying transistors, wherein headroom voltage coupled to a current electrode of each of the amplifying transistors is greater than a supply voltage coupled to gates of the amplifying transistors and the differential signals are capacitively coupled to the cascoded amplifying transistors; and

adjusting voltage levels of the amplified signals to the supply voltage.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2013
From: PELLEY, PERRY H.
To: FREESCALE SEMICONDUCTOR, INC.
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