Memory with power savings for unnecessary reads
View Patent ↗A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
1. A memory device comprising:
a plurality of sense amplifiers each coupled to a sense amplifier control line;
an array of memory cells including a first subset of memory cells;
a plurality of word lines, wherein each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells; and
a plurality of control word lines, wherein each control word line is coupled to a respective one of the memory cells in the first subset of memory cells, and each of the memory cells in the first subset of memory cells stores a first state to generate a sense amplifier control signal on the sense amplifier control line that enables operation of a respective one of the plurality of sense amplifiers and stores a second state to generate the sense amplifier control signal on the sense amplifier control line that disables operation of the respective one of the plurality of sense amplifiers.
2. The device of claim 1 further comprising:
a second subset of memory cells in the array of memory cells, wherein the second subset of memory cells store data.
3. The device of claim 2 wherein:
each of the memory cells in the first subset of memory cells controls access to a respective row of the second subset of memory cells.
4. The device of claim 1 , wherein each of the memory cells in the first subset of memory cells includes:
a first inverter;
a second inverter, wherein an output of the first inverter is coupled to an input of the second inverter, and an output of the second inverter is coupled to an input of the first inverter; and
a pull-down circuit including a first transistor and a second transistor,
the first transistor having a control electrode coupled to the output of the second inverter, and a first current electrode coupled to ground,
the second transistor having a control electrode coupled to a respective one of the word lines, a first current electrode coupled to a second current electrode of the first transistor, and a second current electrode coupled to the respective one of the sense amplifiers.
5. The device of claim 4 further comprising:
a first pass transistor having a first electrode coupled between the output of the first inverter and the input of the second inverter, a second electrode coupled to a complementary write bit line, and a control electrode coupled to a respective one of the control word lines;
a second pass transistor having a first electrode coupled between the output of the second inverter and the input of the first inverter, a second electrode coupled to a write bit line, and a control electrode coupled to the respective one of the control word lines.
6. The device of claim 1 further comprising:
a logic gate having a first input coupled to the sense amplifier control signal, a second input coupled to a sense amplifier clock signal, and an output coupled to the respective one of the plurality of sense amplifiers.
7. The device of claim 1 further comprising:
a variable delay inverter having an input coupled to the sense amplifier control signal and an output coupled to the respective one of the plurality of sense amplifiers.
8. The device of claim 1 further comprising:
a word line driver circuit configured to provide the plurality of word line signals and the plurality of control word line signals.
9. The device of claim 1 wherein the sense amplifier control signal is coupled to control operation of the plurality of sense amplifiers.
10. A memory device comprising:
a plurality of word lines;
an array of memory cells including control memory cells and data storage memory cells, one of the control memory cells and at least one data storage memory cells coupled to each of a respective one of the plurality of word lines, the control memory cells store one of a first state and a second state when a respective word line is selected; and
a sense amplifier, the sense amplifier is enabled to read data from the data storage memory cells along a selected word line when the control memory cell of the selected word line stores the first state and the sense amplifier is disabled from reading data from the at least one data storage memory cell along the selected word line when the control memory cell of the selected memory cell stores the second state.
11. The device of claim 10 further comprising:
an inverter having an input coupled to output of the control memory cells and an output coupled to the sense amplifier.
12. The device of claim 10 further comprising:
a logic gate having a first input coupled to output of the control memory cells, a second input coupled to a sense amplifier clock signal, and an output coupled to the sense amplifier.
13. The device of claim 10 further comprising:
a plurality of control word lines, each of the plurality of control word lines is coupled to a respective one of the control memory cells.
14. The device of claim 13 further comprising:
a word line driver circuit configured to provide signals to the plurality of word lines and the plurality of control word lines.
15. The device of claim 14 , wherein the word line driver circuit further comprises:
a first logic gate having a first input coupled to a row decode signal, a second input coupled to a word line enable signal and an output coupled to a respective one of the plurality of word lines; and
a second logic gate having a first input coupled to the row decode signal, a second input coupled to the word line enable signal, a third input coupled to a write enable signal and an output coupled to a respective one of the plurality of control word lines.
16. A method of operating a memory device having a memory array that includes a plurality of word lines coupled to control memory cells and data storage memory cells, the method comprising:
providing a first word line signal and a control word line signal to one of the control memory cells, wherein the one of the control memory cells and at least one of the data storage memory cells is coupled to a first word line;
if the control memory cell stores a first state, disabling a sense amplifier coupled to the one of the control memory cells; and
if the control memory cell stores a second state, enabling the sense amplifier coupled to the one of the control memory cells.
17. The method of claim 16 further comprising:
setting the first word line signal based on a row decode signal and a word line enable signal.
18. The method of claim 16 further comprising:
setting the control word line signal based on a write enable signal, a row decode signal and a word line enable signal.
19. The method of claim 16 further comprising:
if the control memory cell is in a first state, disabling the sense amplifier before power is used by the sense amplifier to access the at least one of the data storage memory cells.
20. The method of claim 16 further comprising:
using the control word line signal to control operation of pass transistors coupled to cross-coupled inverters in the one of the control memory cells.