Dynamic detection method for latent slow-to-erase bit for high performance and high reliability flash memory
View Patent ↗A method and apparatus for detecting a latent slow bit (e.g., a latent slow-to-erase bit) in a non-volatile memory (NVM) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted. In accordance with at least one embodiment, a number of erase pulses during the erase cycle is counted. In accordance with various embodiments, determinations are made as to whether the maximum number of the soft program pulses has increased at a rate of at least a predetermined minimum rate comparing to a previous erase cycle, whether the maximum number of the soft program pulses has exceeded a predetermined threshold, whether the number of erase pulses has increased comparing to a previous erase cycle, or combinations thereof. In response to such determinations, the NVM is either passed or failed on the basis of the absence or presence of a slow bit in the NVM.
1. A method for detecting a latent slow-to-erase bit in a non-volatile memory (NVM) comprising:
determining a maximum number of soft program pulses used to erase an NVM memory cell during a current erase cycle, the maximum number determined from a plurality of soft program pulse counts of a corresponding plurality of memory cells;
determining a rate of change between the maximum number of the soft program pulses of the current erase cycle as compared to a previous maximum number of the soft program pulses of at least one previous erase cycle; and
asserting a failure indicator in response to the rate of change exceeding a predetermined first threshold.
2. The method of claim 1 wherein the asserting the failure indicator further comprises:
asserting the failure indicator based upon the rate of change exceeding the predetermined first threshold and in response to the maximum number of the soft program pulses used to erase the NVM memory cell during the current erase cycle having exceeded a predetermined second threshold.
3. The method of claim 1 wherein the determining the rate of change comprises:
counting a number of erase pulses during the current erase cycle; and
detecting an increase in the number of the erase pulses as compared to a previous number of the erase pulses during the previous erase cycle.
4. The method of claim 1 further comprising:
prior to the current erase cycle, storing the previous maximum number of the soft program pulses and the previous number of the erase pulses in a test NVM area.
5. The method of claim 4 further comprising:
retrieving the previous maximum number of the soft program pulses and the previous number of the erase pulses from the test NVM area.
6. The method of claim 1 wherein the predetermined first threshold is at least a 20% increase, as compared to the previous maximum number of the soft program pulses in the previous erase cycle.
7. The method of claim 1 wherein the predetermined first threshold is at least a 50% increase, as compared to the previous maximum number of the soft program pulses in the previous erase cycle.
8. A non-volatile memory (NVM) comprising:
a bit cell array comprising a plurality of bit cells for storing a plurality of bits, the bit cell array comprising a test memory area for pulse count storage; and
an NVM controller coupled to the bit cell array, the NVM controller configured for causing the NVM controller to determine a maximum number of soft program pulses used to erase a bit cell of the plurality of bit cells during a current erase cycle, to determine a rate of change between the maximum number of the soft program pulses of the current erase cycle as compared to a previous maximum number of the soft program pulses of at least one previous erase cycle, and to assert a failure signal to fail the NVM based upon the rate of change exceeding a predetermined first threshold.
9. The NVM of claim 8 wherein the NVM controller is further configured to assert the failure signal indicative of failing the NVM based upon the rate of change exceeding the predetermined first threshold and in response to the maximum number of the soft program pulses having exceeded a predetermined second threshold.
10. The NVM of claim 9 wherein the NVM controller is further configured for counting a number of erase pulses during the erase cycle and for detecting an increase in the number of the erase pulses as compared to a previous number of the erase pulses during the previous erase cycle.
11. The NVM of claim 10 wherein the NVM controller is further configured to store the previous maximum number of the soft program pulses and the previous number of the erase pulses in a test NVM area.
12. The NVM of claim 10 wherein the NVM controller is further configured to retrieve the previous maximum number of the soft program pulses and the previous number of the erase pulses from the test NVM area.
13. The NVM of claim 8 wherein the predetermined first threshold is at least a 20% increase, as compared to the previous maximum number of the soft program pulses in the previous erase cycle.
14. The NVM of claim 8 wherein the predetermined first threshold is at least a 50% increase, as compared to the previous maximum number of the soft program pulses in the previous erase cycle.
15. A method comprising:
detecting a latent slow-to-erase bit in a non-volatile memory (NVM) in response to a change between a first maximum soft program pulse count during a previous erase cycle and a second maximum soft program pulse count during an erase cycle; and
failing the NVM in response to the detecting the latent slow-to-erase bit.
16. The method of claim 15 wherein the detecting the latent slow-to-erase bit in the NVM further comprises:
detecting the latent slow-to-erase bit in the NVM in response to a maximum soft program pulse count value having exceeded a predetermined threshold, wherein the maximum soft program pulse count value is selected from a group consisting of the first maximum soft program pulse count and the second maximum soft program pulse count.
17. The method of claim 16 wherein the detecting the latent slow-to-erase bit in the NVM further comprises:
detecting the latent slow-to-erase bit in the NVM in response to a change in an erase pulse count value between a first erase pulse count and a second erase pulse count.
18. The method of claim 16 wherein the predetermined threshold is programmable.
19. The method of claim 15 wherein the first maximum soft program pulse count and the second maximum soft program pulse count are stored in a test NVM area of the NVM to allow multiple instances of storing the maximum soft program pulse counts in the test NVM area to occur between erasures of the test NVM area.
20. The method of claim 15 wherein a parameter determinative of the change in the maximum soft program pulse counts between the first maximum soft program pulse count and the second maximum soft program pulse count sufficient for the detecting the latent slow-to-erase bit in the NVM is programmable.