Method and apparatus for detecting a collision between multiple threads of execution for accessing a memory array
View Patent ↗A method includes determining, for a first thread of execution, a first speculative decoded operands signal and determining, for a second thread of execution, a second speculative decoded operands signal. The method further includes determining, for the first thread of execution, a first constant and determining, for the second thread of execution, a second constant. The method further compares the first speculative decoded operands signal to the second speculative decoded operands signal and uses the first and second constant to detect a wordline collision for accessing the memory array.
1. A computer-implemented method for detecting a collision between multiple threads of execution for accessing a memory array, the method comprising:
determining, for a first thread of execution, a first speculative decoded operands value by summing a first subset of consecutive bits from a first base operand and a first subset of consecutive bits from a first offset operand;
determining, for a second thread of execution, a second speculative decoded operands value by summing a first subset of consecutive bits from a second base operand and a first subset of consecutive bits from a second offset operand;
determining, for the first thread of execution, a first least significant bit value based on a sum of a second subset of bits from the first base operand and a second subset of bits from the first offset operand;
determining, for the second thread of execution, a second least significant bit value based on a sum of a second subset of bits from the second base operand and a second subset of bits from the second offset operand; and
determining a word line collision between the first and second threads is indicated when the first speculative decoded operands value matches the second speculative decoded operands value and the first and second least significant bit values correspond to the same value.
2. The method of claim 1 , wherein an even wordline collision, between the first and second threads of execution, for accessing the memory array is indicated when the first and second least significant bit values each have a value that is equivalent to a binary zero, and wherein an odd wordline collision, between the first and second threads of execution, for accessing the memory array is indicated when the first and second least significant bit values each have a value that is equivalent to a binary one.
3. The method of claim 1 , wherein an even wordline collision is indicated when the first and second least significant bit values both correspond to a binary zero.
4. The method of claim 1 , wherein an odd wordline collision is indicated when the first and second least significant bit values both correspond to a binary one.
5. The method of claim 1 , wherein the computer-implemented method is performed in parallel with summing the first base operand with the first offset operand to determine a first effective memory address and with summing the second base operand with the second offset operand to determine a second effective memory address.
6. Memory array access and collision detection apparatus comprising:
an operands decoding circuit configured to:
determine, for a first thread of execution, a first speculative decoded operands signal based on a first subset of consecutive bits from a first base operand and a first subset of consecutive bits from a first offset operand; and
determine, for a second thread of execution, a second speculative decoded operands signal based on a first subset of consecutive bits from a second base operand and a first subset of consecutive bits from a second offset operand;
a first adder circuit configured to determine, for the first thread of execution, a first least significant bit value based on a sum of a second subset of bits from the first base operand and a second subset of bits from the first offset operand;
a second adder circuit configured to determine, for the second thread of execution, a second constant based on a sum of a second subset of bits from the second base operand and a second subset of bits from the second offset operand; and
a third logic circuit coupled to the operands decoding circuit and to the first and second adder circuits, wherein the third logic circuit is configured to detect a wordline collision when the first speculative decoded operands signal matches the second speculative decoded operands signal and the first least significant bit value is equal to the second least significant bit value.
7. The apparatus of claim 6 , wherein the third logic circuit is further configured to generate a wordline collision signal indicating a detected wordline collision between the first and second threads of execution for accessing the memory array, the system further comprising:
a collision avoidance circuit coupled between the third logic circuit and the memory array, wherein the collision avoidance circuit is configured to receive the wordline collision signal, a first wordline determined for the first thread of execution, and a second wordline determined for the second thread of execution and to prevent or delay the first or second wordline access to the memory array.
8. The apparatus of claim 6 , wherein the third logic circuit comprises a multiplexer circuit, wherein the multiplexer circuit is configured to use the first and second least significant bits as first and second selection bits to detect the wordline collision when the first speculative decoded operands signal matches the second speculative decoded operands signal.
9. The apparatus of claim 8 , wherein the multiplexer is configured to detect the wordline collision when the first least significant bit value is equal to the second least significant bit value.
10. A computer-implemented method for detecting a collision between multiple threads of execution for accessing a memory array, the method comprising:
determining, for a first thread of execution, a first speculative decoded operands signal based on a first subset of consecutive bits from a first base operand and a first subset of consecutive bits from a first offset operand;
determining, for a second thread of execution, a second speculative decoded operands signal based on a first subset of consecutive bits from a second base operand and a first subset of consecutive bits from a second offset operand; and
comparing the first speculative decoded operands signal to the second speculative decoded operands signal, and when the first speculative decoded operands signal and the second speculative decoded operands signal have an equivalent value, detecting a wordline collision between the first and second threads when a least significant bit value calculated by summing a second subset of bits from the first base operand with a second subset of bits from the first offset operand is equal to a second least significant value calculated by summing a second subset of bits from the second base operand and a second subset of bits from the second offset operand.
11. The method of claim 10 , wherein an even wordline collision is indicated when the first and second least significant bit values correspond to a binary zero and when the first and second speculative decoded operands signals correspond to a same even numbered value.
12. The method of claim 10 , wherein an odd wordline collision is indicated when the first and second least significant bit values correspond to a binary one and when the first and second speculative decoded operands signals correspond to a same odd numbered value.
13. The method of claim 1 , further comprising providing collision avoidance in response to detecting the wordline collision, wherein the first thread and the second thread attempt to access the same wordline at the same time.