Microelectromechanical system devices having through substrate vias and methods for the fabrication thereof
View Patent ↗Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via.
1. A method of fabricating of a Microelectromechanical Systems (“MEMS”) device, comprising:
forming at least one via opening extending into a substrate wafer;
depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via;
bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer;
forming an electrical connection between the via and the electrically-conductive transducer layer;
thinning the substrate wafer to reveal the via through a bottom surface of the substrate wafer;
after thinning the substrate wafer, producing a backside conductor over the bottom surface of the substrate wafer electrically coupled to the via;
forming a patterned interconnect layer over the substrate wafer; and
forming a sacrificial dielectric layer over the patterned interconnect layer prior to bonding the substrate wafer to the transducer wafer.
2. The method of claim 1 further comprising patterning a layer of the transducer wafer to define a primary MEMS transducer structure after bonding the substrate wafer to the transducer wafer.
3. The method of claim 1 wherein bonding comprises fusion bonding the transducer wafer to the sacrificial dielectric layer.
4. The method of claim 1 further comprising:
patterning the electrically-conductive transducer layer after bonding the substrate wafer to the transducer wafer; and
removing at least a portion of the sacrificial dielectric layer through an opening formed in the electrically-conductive transducer layer during patterning thereof.
5. The method of claim 1 wherein forming an electrical connection between the via and the electrically-conductive transducer layer comprises producing an electrically-conductive plug electrically coupling the electrically-conductive transducer layer to the via after bonding the substrate wafer to the transducer wafer.
6. The method of claim 1 wherein an electrical connection is formed between the via and the electrically-conductive transducer layer after bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer.
7. The method of claim 1 further comprising attaching a MEMS cap over the primary transducer structure, wherein thinning the substrate comprises grinding the backside of the substrate wafer after attachment of the MEMS cap to impart the substrate with a predetermined thickness.
8. The method of claim 1 further comprising forming at least one embedded lithographical alignment feature extending into the substrate and visible through the backside of the substrate wafer after thinning thereof.
9. The method of claim 8 wherein forming the at least one embedded lithographical alignment feature comprises:
forming an alignment feature opening extending into the substrate wafer; and
depositing a fill material into the alignment feature opening to produce the embedded lithographical alignment feature within the substrate;
wherein the embedded lithographical alignment feature is revealed through the bottom surface of the substrate along with the via after thinning of the substrate wafer.
10. The method of claim 9 wherein the fill material comprises polycrystalline silicon, and wherein the alignment feature opening is filled, at least in substantial part, during deposition of the body of electrically-conductive material over the sacrificial layer and into the via opening.
11. The method of claim 1 wherein the backside conductor comprises a backside bond pad, and wherein the method further comprises forming at least one interconnect line over the backside of the substrate wafer electrically coupling the backside bond pad to the via.
12. The method of claim 1 further comprising packaging the MEMS device utilizing a chip scale package after producing the backside conductor on the backside of the substrate electrically coupled to the via.
13. The method of claim 5 further comprising patterning a layer of the transducer wafer to define a primary MEMS transducer structure after bonding the substrate wafer to the transducer wafer.
14. The method of claim 5 further comprising forming at least one embedded lithographical alignment feature extending into the substrate and visible through the backside of the substrate wafer after thinning thereof.
15. A method of fabricating of a Microelectromechanical Systems (“MEMS”) device, comprising:
forming at least one via opening extending into a substrate wafer;
depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via;
bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer;
producing an electrically-conductive plug electrically coupling the electrically-conductive transducer layer to the via after bonding the substrate wafer to the transducer wafer;
thinning the substrate wafer to reveal the via through a bottom surface of the substrate wafer; and
after thinning the substrate wafer, producing a backside conductor over the bottom surface of the substrate wafer electrically coupled to the via;
wherein producing an electrically-conductive plug comprises:
forming a sacrificial dielectric layer over the substrate wafer prior to bonding the substrate wafer to the transducer wafer;
forming a patterned interconnect layer over the substrate wafer having a region in ohmic contact with the via;
etching an opening through the electrically-conductive transducer layer, through the sacrificial dielectric layer, and to the region of the patterned interconnect layer in ohmic contact with the via; and
filling the opening with an electrically-conductive material to produce the electrically-conductive plug.
16. The method of claim 15 wherein filling the opening comprises:
depositing polycrystalline silicon into the opening and over an upper surface of the electrically-conductive transducer layer to produce the electrically-conductive plug and an electrically-conductive overburden layer; and
removing the electrically-conductive overburden layer from over the electrically-conductive transducer layer using a polishing process.
17. The method of claim 15 further comprising:
forming an interconnect layer over the substrate wafer prior to bonding the substrate wafer to the transducer wafer; and
patterning the interconnect layer to define at least one interconnect line in ohmic contact with the via.
18. A method of fabricating of a Microelectromechanical Systems (“MEMS”) device, comprising:
bonding a transducer wafer to a substrate wafer, the substrate wafer comprising at least one via extending into a substrate and a sacrificial dielectric layer formed over an upper surface of the substrate, the transducer wafer comprising an unpatterned transducer layer;
forming an electrically-conductive plug electrically coupling the unpatterned transducer layer to the via after bonding the transducer wafer to the substrate wafer;
patterning the unpatterned transducer layer to define a primary transducer structure;
removing at least a portion of the sacrificial dielectric layer through at least one opening formed in the transducer layer during patterning thereof to release the primary transducer structure;
grinding the backside of the substrate to remove a predetermined thickness therefrom reveal the via through a bottom surface of the substrate wafer; and
producing at least one backside conductor over the bottom surface of the substrate wafer electrically coupled to the via.
19. The method of claim 18 wherein the substrate wafer comprises an embedded alignment feature, and wherein grinding comprises grinding the backside of the substrate to remove a predetermined thickness therefrom and reveal the via and the embedded alignment feature through a bottom surface of the substrate wafer.
20. The method of claim 18 wherein producing at least one backside conductor comprises producing a backside bond pad and an interconnect line over the bottom surface of the substrate wafer, the interconnect line electrically coupling the backside bond pad to the via.