Voltage scale-down circuit
View Patent ↗A circuit for scaling down first and second input voltages includes first and second voltage scale-down circuits that scale down the first and second input voltages, respectively. The first voltage scale-down circuit includes a transistor that receives the first input voltage at its gate and, operating in a source-follower configuration, scales down the first input voltage to generate a first output voltage at its source. The second voltage scale-down circuit is identical to the first voltage scale-down circuit and generates a second output voltage based on the second input voltage.
1. A system for scaling down first and second input voltages and generating first and second output voltages, comprising:
a first voltage scale-down circuit for receiving and scaling down the first input voltage to generate the first output voltage, comprising:
a first transistor ( 208 ) having a drain terminal for receiving a first supply voltage and a gate terminal for receiving the first input voltage;
a second transistor ( 210 ) having a source terminal connected to a source terminal of the first transistor;
a third transistor ( 212 ) having a drain terminal connected to the source terminals of the first and second transistors, a gate terminal connected to a gate terminal of the second transistor and to the first supply voltage, and a source terminal connected to the gate terminals of the second and third transistors;
a fourth transistor ( 214 ) having a gate terminal connected to the drain terminal of the third transistor;
a fifth transistor ( 216 ) having a source terminal for receiving the first supply voltage and a drain terminal connected to a drain terminal of the fourth transistor;
a sixth transistor ( 218 ) having a source terminal for receiving the first supply voltage and a gate terminal connected to the gate terminal of the fifth transistor;
a seventh transistor ( 220 ) having a source terminal for receiving a second supply voltage, a gate terminal connected to the gate terminals of the fifth and sixth transistors, and a drain terminal connected to a drain terminal of the sixth transistor;
an eighth transistor ( 222 ) having drain and gate terminals connected to the drain terminals of the sixth and seventh transistors and a source terminal connected to the drain terminals of the fourth and fifth transistors;
a ninth transistor ( 224 ) having a source terminal connected to the source terminal of the fourth transistor, a drain terminal for receiving the first supply voltage, a gate terminal connected to a drain terminal of the second transistor, and a body terminal connected to the source terminals of the first and second transistors;
a tenth transistor ( 226 ) having a drain terminal connected to the source terminals of the fourth and ninth transistors, a gate terminal connected to the gate terminals of the first and ninth transistors for receiving the first input voltage, and a source terminal for generating a first intermediate signal;
a first resistor ( 228 ) having a first terminal connected to the source terminal of the tenth transistor for receiving the first intermediate signal and a second terminal connected to a body terminal of the tenth transistor for generating a second intermediate signal;
a second resistor ( 230 ) having a first terminal connected to the second terminal of the first resistor for receiving the second intermediate signal and a second terminal for generating the first output voltage;
a third resistor ( 232 ) having a first terminal connected to the second terminal of the second resistor for receiving the first output voltage; and
an eleventh transistor ( 206 ) having a drain terminal connected to a second terminal of the third resistor, a gate terminal for receiving a third input voltage, and a source terminal shorted to ground; and
a second voltage scale-down circuit connected to the drain terminal of the eleventh transistor for receiving and scaling down the second input voltage to generate the second output voltage, comprising:
a twelfth transistor ( 234 ) having a drain terminal for receiving a first supply voltage and a gate terminal for receiving the second input voltage;
a thirteenth transistor ( 236 ) having a source terminal connected to a source terminal of the twelfth transistor;
a fourteenth transistor ( 238 ) having a drain terminal connected to the source terminals of the twelfth and thirteenth transistors, a gate terminal connected to a gate terminal of the thirteenth transistor and to the first supply voltage, and a source terminal connected to the gate terminals of the thirteenth and fourteenth transistors;
a fifteenth transistor ( 240 ) having a gate terminal connected to the drain terminal of the fourteenth transistor;
a sixteenth transistor ( 242 ) having a source terminal for receiving the first supply voltage and a drain terminal connected to a drain terminal of the fifteenth transistor;
a seventeenth transistor ( 244 ) having a source terminal for receiving the first supply voltage and a gate terminal connected to the gate terminal of the sixteenth transistor;
an eighteenth transistor ( 246 ) having a source terminal for receiving the second supply voltage, a gate terminal connected to the gate terminals of the sixteenth and seventeenth transistors, and a drain terminal connected to a drain terminal of the seventeenth transistor;
a nineteenth transistor ( 248 ) having drain and gate terminals connected to the drain terminals of the seventeenth and eighteenth transistors and a source terminal connected to the drain terminals of the fifteenth and sixteenth transistors;
a twentieth transistor ( 250 ) having a source terminal connected to the source terminal of the fifteenth transistor, a drain terminal for receiving the first supply voltage, a gate terminal connected to a drain terminal of the thirteenth transistor, and a body terminal connected to the source terminals of the twelfth and thirteenth transistors;
a twenty-first transistor ( 252 ) having a drain terminal connected to the source terminals of the fifteenth and twentieth transistors, a gate terminal connected to the gate terminals of the twelfth and twentieth transistors for receiving the first input voltage, and a source terminal for generating a third intermediate signal;
a fourth resistor ( 254 ) having a first terminal connected to the source terminal of the twenty-first transistor for receiving the third intermediate signal and a second terminal connected to a body terminal of the twenty-first transistor for generating a fourth intermediate signal;
a fifth resistor ( 256 ) having a first terminal connected to the second terminal of the fourth resistor for receiving the fourth intermediate signal and a second terminal for generating the second output voltage; and
a sixth resistor ( 258 ) having a first terminal connected to the second terminal of the fifth resistor for receiving the second output voltage.
2. The system of claim 1 , wherein the first, second, seventh, ninth, twelfth, thirteenth, eighteenth, and twentieth transistors are p-channel metal-oxide semiconductor (PMOS) transistors.
3. The system of claim 1 , wherein the third, fourth, fifth, sixth, eighth, tenth, eleventh, fourteenth, fifteenth, sixteenth, seventeenth, nineteenth, and twenty-first transistors are n-channel metal-oxide semiconductor (NMOS) transistors.
4. A system for scaling down first and second input voltages and generating first and second output voltages, the system comprising:
a first voltage scale-down circuit for receiving and scaling down the first input voltage to generate the first output voltage, comprising:
a first transistor having a drain terminal for receiving a first supply voltage, and a gate terminal for receiving the first input voltage;
a second transistor having a source terminal connected to a source terminal of the first transistor;
a third transistor having a drain terminal connected to the source terminals of the first and second transistors, a gate terminal connected to a gate terminal of the second transistor and to the first supply voltage, and a source terminal connected to the gate terminals of the second and third transistors;
a fourth transistor having a gate terminal connected to the drain terminal of the third transistor;
a fifth transistor having a source terminal for receiving the first supply voltage and a drain terminal connected to a drain terminal of the fourth transistor;
a sixth transistor having a source terminal for receiving the first supply voltage and a gate terminal connected to the gate terminal of the fifth transistor;
a seventh transistor having a source terminal for receiving a second supply voltage, a gate terminal connected to the gate terminals of the fifth and sixth transistors, and a drain terminal connected to a drain terminal of the sixth transistor;
an eighth transistor having drain and gate terminals connected to the drain terminals of the sixth and seventh transistors, and a source terminal connected to the drain terminals of the fourth and fifth transistors;
a ninth transistor having a source terminal connected to the source terminal of the fourth transistor, a drain terminal for receiving the first supply voltage, a gate terminal connected to a drain terminal of the second transistor, and a body terminal connected to the source terminals of the first and second transistors;
a tenth transistor having a drain terminal connected to the source terminals of the fourth and ninth, a gate terminal connected to the gate terminals of the first and ninth transistors for receiving the first input voltage, and a source terminal for generating a first intermediate signal;
a first resistor having a first terminal connected to the source terminal of the tenth transistor for receiving the first intermediate signal, and a second terminal connected to a body terminal of the tenth transistor for generating a second intermediate signal;
a second resistor having a first terminal connected to the second terminal of the first resistor for receiving the second intermediate signal, and a second terminal for generating the first output voltage; and
a third resistor having a first terminal connected to the second terminal of the second resistor for receiving the first output voltage;
an eleventh transistor having a drain terminal connected to a second terminal of the third resistor, a gate terminal for receiving a third input voltage, and a source terminal shorted to ground; and
a second voltage scale-down circuit, connected to the drain terminal of the eleventh transistor, for receiving and scaling down the second input voltage to generate the second output voltage.
5. The system of claim 4 , wherein the second voltage scale-down circuit includes:
a twelfth transistor having a drain terminal for receiving a first supply voltage, and a gate terminal for receiving the second input voltage;
a thirteenth transistor having a source terminal connected to a source terminal of the twelfth transistor;
a fourteenth transistor having a drain terminal connected to the source terminals of the twelfth and thirteenth transistors, a gate terminal connected to a gate terminal of the thirteenth transistor and to the first supply voltage, and a source terminal connected to the gate terminals of the thirteenth and fourteenth transistors;
a fifteenth transistor having a gate terminal connected to the drain terminal of the fourteenth transistor;
a sixteenth transistor having a source terminal for receiving the first supply voltage, and a drain terminal connected to a drain terminal of the fifteenth transistor;
a seventeenth transistor having a source terminal for receiving the first supply voltage, and a gate terminal connected to the gate terminal of the sixteenth transistor;
an eighteenth transistor having a source terminal for receiving the second supply voltage, a gate terminal connected to the gate terminals of the sixteenth and seventeenth transistors, and a drain terminal connected to a drain terminal of the seventeenth transistor;
a nineteenth transistor having drain and gate terminals connected to the drain terminals of the seventeenth and eighteenth transistors, and a source terminal connected to the drain terminals of the fifteenth and sixteenth transistors;
a twentieth transistor having a source terminal connected to the source terminal of the fifteenth transistor, a drain terminal for receiving the first supply voltage, and a gate terminal connected to a drain terminal of the thirteenth transistor;
a twenty-first transistor having a drain terminal connected to the source terminals of the fifteenth and twentieth transistors, a gate terminal connected to the gate terminals of the twelfth and twentieth transistors for receiving the first input voltage, and a source terminal for generating a third intermediate signal;
a fourth resistor having a first terminal connected to the source terminal of the twenty-first transistor for receiving the third intermediate signal and a second terminal connected to a body terminal of the twenty-first transistor for generating a fourth intermediate signal;
a fifth resistor having a first terminal connected to the second terminal of the fourth resistor for receiving the fourth intermediate signal and a second terminal for generating the second output voltage; and
a sixth resistor having a first terminal connected to the second terminal of the fifth resistor for receiving the second output voltage.
6. The system of claim 5 , wherein the first, second, seventh, ninth, twelfth, thirteenth, eighteenth, and twentieth transistors are p-channel metal-oxide semiconductor (pMOS) transistors.
7. The system of claim 5 , wherein the third, fourth, fifth, sixth, eighth, tenth, eleventh, fourteenth, fifteenth, sixteenth, seventeenth, nineteenth, and twenty-first transistors are n-channel metal-oxide semiconductor (NMOS) transistors.
8. A differential receiver for generating a differential output signal, comprising:
a first voltage scale-down circuit for receiving and scaling down the first input voltage to generate the first output voltage, comprising:
a first transistor having a drain terminal for receiving a first supply voltage and a gate terminal for receiving the first input voltage;
a second transistor having a source terminal connected to a source terminal of the first transistor;
a third transistor having a drain terminal connected to the source terminals of the first and second transistors, a gate terminal connected to a gate terminal of the second transistor and to the first supply voltage, and a source terminal connected to the gate terminals of the second and third transistors;
a fourth transistor having a gate terminal connected to the drain terminal of the third transistor;
a fifth transistor having a source terminal for receiving the first supply voltage and a drain terminal connected to a drain terminal of the fourth transistor;
a sixth transistor having a source terminal for receiving the first supply voltage and a gate terminal connected to the gate terminal of the fifth transistor;
a seventh transistor having a source terminal for receiving a second supply voltage, a gate terminal connected to the gate terminals of the fifth and sixth transistors, and a drain terminal connected to a drain terminal of the sixth transistor;
an eighth transistor having drain and gate terminals connected to the drain terminals of the sixth and seventh transistors and a source terminal connected to the drain terminals of the fourth and fifth transistors;
a ninth transistor having a source terminal connected to the source terminal of the fourth transistor, a drain terminal for receiving the first supply voltage, a gate terminal connected to a drain terminal of the second transistor, and a body terminal connected to the source terminals of the first and second transistors;
a tenth transistor having a drain terminal connected to the source terminals of the fourth and ninth transistors, a gate terminal connected to the gate terminals of the first and ninth transistors for receiving the first input voltage, and a source terminal for generating a first intermediate signal;
a first resistor having a first terminal connected to the source terminal of the tenth transistor for receiving the first intermediate signal and a second terminal connected to a body terminal of the tenth transistor for generating a second intermediate signal;
a second resistor having a first terminal connected to the second terminal of the first resistor for receiving the second intermediate signal and a second terminal for generating the first output voltage; and
a third resistor having a first terminal connected to the second terminal of the second resistor for receiving the first output voltage;
an eleventh transistor having a drain terminal connected to a second terminal of the third resistor, a gate terminal for receiving a third input voltage, and a source terminal shorted to ground; and
a second voltage scale-down circuit connected to the drain terminal of the eleventh transistor for receiving and scaling down the second input voltage to generate the second output voltage, comprising:
a twelfth transistor having a drain terminal for receiving a first supply voltage and a gate terminal for receiving the second input voltage;
a thirteenth transistor having a source terminal connected to a source terminal of the twelfth transistor;
a fourteenth transistor having a drain terminal connected to the source terminals of the twelfth and thirteenth transistors, a gate terminal connected to a gate terminal of the thirteenth transistor and to the first supply voltage, and a source terminal connected to the gate terminals of the thirteenth and fourteenth transistors;
a fifteenth transistor having a gate terminal connected to the drain terminal of the fourteenth transistor;
a sixteenth transistor having a source terminal for receiving the first supply voltage, and a drain terminal connected to a drain terminal of the fifteenth transistor;
a seventeenth transistor having a source terminal for receiving the first supply voltage, and a gate terminal connected to the gate terminal of the sixteenth transistor;
an eighteenth transistor having a source terminal for receiving the second supply voltage, a gate terminal connected to the gate terminals of the sixteenth and seventeenth transistors, and a drain terminal connected to a drain terminal of the seventeenth transistor;
a nineteenth transistor having drain and gate terminals connected to the drain terminals of the seventeenth and eighteenth transistors and a source terminal connected to the drain terminals of the fifteenth and sixteenth transistors;
a twentieth transistor having a source terminal connected to the source terminal of the fifteenth transistor, a drain terminal for receiving the first supply voltage, a gate terminal connected to a drain terminal of the thirteenth transistor, and a body terminal connected to the source terminals of the twelfth and thirteenth transistors;
a twenty-first transistor having a drain terminal connected to the source terminals of the fifteenth and twentieth transistors, a gate terminal connected to the gate terminals of the twelfth and twentieth transistors for receiving the first input voltage, and a source terminal for generating a third intermediate signal;
a fourth resistor having a first terminal connected to the source terminal of the twenty-first transistor for receiving the third intermediate signal and a second terminal connected to a body terminal of the twenty-first transistor for generating a fourth intermediate signal;
a fifth resistor having a first terminal connected to the second terminal of the fourth resistor for receiving the fourth intermediate signal and a second terminal for generating the second output voltage; and
a sixth resistor having a first terminal connected to the second terminal of the fifth resistor for receiving the second output voltage; and
a differential amplifier having a first input terminal connected to the first voltage scale-down circuit for receiving the first output voltage, a second input terminal connected to the second voltage scale-down circuit for receiving the second output voltage, and an output terminal for generating the differential output signal.
9. The differential receiver of claim 8 , wherein the differential output signal is provided to an input/output (I/O) circuit including a universal serial bus (USB).