Granted Patent B2

US 9,129,700 · App. 13/746,841 · Granted Sep 8, 2015

Abstract

Claims (50)

1. A method of soft programming a non-volatile memory (NVM) having an array of bit cells, wherein the soft programming occurs after erasing the bit cells, comprising:

determining over-erased bit cells;

detecting a temperature;

providing a first soft program gate voltage based on the temperature;

performing soft programming on the over-erased bit cells using the first soft program gate voltage;

identifying any remaining over-erased bit cells;

if there are any remaining over-erased bit cells, performing soft programming on the remaining over-erased bit cells using a second soft program gate voltage incremented from the first soft program gate voltage.

2. The method of claim 1 , wherein the detecting a temperature comprises:

using a temperature sensor to provide a temperature-related voltage; and

coupling the temperature-related voltage to an analog to digital converter.

3. The method of claim 2 , wherein the providing a first soft program gate voltage comprises:

providing a voltage select signal responsive to an output of the analog to digital signal; and

using a programmable voltage generator to provide the first soft program gate voltage responsive to the voltage select signal.

4. The method of claim 3 , wherein the performing soft programming on the remaining over-erased bit cells is further characterized by incrementing the voltage select signal to cause the programmable voltage generator to increment the first soft program gate voltage to obtain the second soft program gate voltage.

5. The method of claim 1 , further comprising:

identifying any further remaining over-erased bit cells;

if there are any further remaining over-erased bit cells, performing soft programming on the further remaining over-erased bit cells using a third soft program gate voltage incremented from the second soft program gate voltage.

6. The method of claim 1 , further comprising continuing to determine if over-erased bit cells are resulting from soft programming and incrementing an immediately preceding soft program voltage until:

all of the over erased bit cells are sufficiently soft programmed;

the maximum number of soft programming pulses has been applied; or

the maximum magnitude of the soft program gate voltage has been used for soft programming.

7. The method of claim 1 , wherein the determining the over-erased bit cells comprises determining which bit cells have a threshold voltage below a predetermined voltage.

8. The method of claim 1 , wherein a magnitude of the increment is a function of the temperature.

9. A non-volatile memory (NVM), comprising:

an array of bit cells;

a temperature sensor;

a soft programming gate voltage selector coupled to the temperature sensor;

soft program logic coupled to coupled to the soft programming gate voltage selector, wherein the soft program logic controls soft programming of the bit cells;

a programmable gate voltage generator coupled to the soft program logic;

a row decoder coupled to the programmable gate voltage generator, the array of bit cells, and the soft program logic; and

column logic coupled to the soft program logic and the array of bit cells,

wherein the soft program logic uses the programmable gate voltage generator to provide a soft program gate voltage to the row decoder during a soft programming operation, and

wherein the soft program gate voltage is selected based on a temperature sensed by the temperature sensor.

10. The NVM of claim 9 , wherein the soft program logic runs soft programming on bit cells that are over-erased.

11. The NVM of claim 10 , wherein the soft program logic increments the soft program gate voltage when over-erased bit cells remain after a soft program operation for a subsequent program operation on bit cells still over-programmed.

12. The NVM of claim 11 , wherein the soft program logic completes a soft program process when all of the bit cells have a threshold voltage above a predetermined threshold voltage.

13. The NVM of claim 12 , wherein the temperature sensor provides a digital output representative of the temperature sensed.

14. The NVM of claim 13 , wherein the soft program logic determines that the soft program process has failed if a maximum number of soft program pulses have been applied to a bit cell or if a maximum soft program pulse voltage has been applied.

15. The NVM of claim 11 , further comprising at least one of a group consisting of: a magnitude that the soft program logic increments the soft program gate voltage is based on the temperature, and a maximum soft programming voltage is based on the temperature.

16. The NVM of claim 9 , wherein the bit cells comprise one of group consisting of NOR type NVM cells, one T type cells, one and half T type cells, two T type cells, floating gate type cells, nanocrystal type cells.

17. A method of erasing a non-volatile memory (NVM) having a plurality of NVM bit cells, comprising:

performing an erase step that causes a first portion of the bit cells to have a sufficiently low threshold voltage for reliable sensing and a second portion of the bit cells to be over-erased;

sensing a temperature;

providing a first soft program gate voltage based on the temperature;

performing a soft program operation on the over-erased bit cells using the first soft program gate voltage.

18. The method of claim 17 , further comprising:

identifying remaining over-erased bit cells;

performing a soft program operation on the remaining over-erased bit cells using a second soft program gate voltage that is greater than the first soft program gate voltage.

19. The method of claim 18 , wherein the second soft program gate voltage is incremented above the first soft program gate voltage by an amount based on the temperature.

20. The method of claim 18 , wherein the second soft program gate voltage is incremented above the first soft program gate voltage by a predetermined amount.

Assignments (21)