Gate security feature
View Patent ↗An anti-counterfeiting security circuit is incorporated into an authentic integrated circuit device to induce failure in a counterfeited integrated circuit device by forming the security circuit (e.g., 21, 31, 41, 51 ) with one or more operatively inert high-k metal gate transistors (e.g., HKMG PMOS 112 ) having switched or altered work function metal layers ( 82 ) where the security circuit defines a first electrical function with the one or more operatively inert high-k metal gate transistors and defines a second different electrical function if the one or more operatively inert high-k metal gate transistors were instead fabricated as operatively functional high-k metal gate transistors of the first polarity type with a work function metal layer of the first polarity type, the security circuit would define a second different electrical function.
1. A method for implementing hardware security in an integrated circuit device comprising:
obtaining an integrated circuit device comprising a security circuit defining a first electrical function and formed with at least one or more operatively non-functional high-k metal gate transistors of a first polarity type having a work function metal layer suitable for a transistor of a second, opposite polarity type, where, if the one or more operatively non-functional high-k metal gate transistors were replaced with operatively functional high-k metal gate transistors of the first polarity type with a work function metal layer suitable for a transistor of the first polarity type, the security circuit would define a second electrical function that is different from the first electrical function.
2. The method of claim 1 , where obtaining an integrated circuit device comprises:
providing a wafer comprising a plurality of sacrificial transistor gate structures formed over the substrate;
forming a dielectric layer having a substantially flat upper surface which exposes an upper surface of the plurality of sacrificial transistor gate structures;
selectively removing the plurality of sacrificial transistor gate structures to form a plurality of gate electrode openings in the dielectric layer;
selectively forming first and second work function metal layers in the plurality of gate electrode openings and on the high-k gate dielectric layer to define a plurality of functional NMOS and PMOS transistors and one or more operatively non-functional high-k metal gate transistors; and
forming a metal layer over the first and second work function metal layers in the plurality of gate electrode openings; and
polishing the metal layer down to at least the dielectric layer to define a plurality of high-k metal gate electrodes for the functional NMOS and PMOS transistors and one or more operatively non-functional high-k metal gate transistors.
3. The method of claim 2 , where selectively forming first and second work function metal layers comprises forming an NMOS gate metal work function layer in one or more PMOS transistors gate electrode openings to define one or more operatively non-functional high-k metal gate PMOS transistors.
4. The method of claim 3 , where forming the NMOS gate metal work function layer comprises depositing a layer of TiAlN in one or more PMOS transistors gate electrode openings to define one or more operatively non-functional high-k metal gate PMOS transistors.
5. The method of claim 2 , where selectively forming first and second work function metal layers comprises forming a PMOS gate metal work function layer in one or more NMOS transistors gate electrode openings to define one or operatively non-functional more high-k metal gate NMOS transistors.
6. The method of claim 5 , where forming the PMOS gate metal work function layer comprises depositing a layer of TiN in one or more NMOS transistors gate electrode openings to define one or more operatively non-functional high-k metal gate NMOS transistors.
7. The method of claim 1 , where the security circuit comprises a pull down circuit for a first node connected to a pull down reference voltage by a plurality of pull down transistors comprising one or more first functionally operative high-k metal gate transistors connected between the first node and the pull down reference voltage, and one or more second operatively non-functional high-k metal gate transistors connecting the first node to the pull down reference voltage.
8. The method of claim 1 , where the security circuit comprises a latch circuit for connecting one or more input ports to an internal node through a plurality of input circuits, where at least one of the plurality of input circuits comprises one or more operatively non-functional high-k metal gate transistors to prevent an input port from connecting to the internal node.
9. The method of claim 1 , where the security circuit comprises a pull up circuit connecting an internal node to a pull up reference voltage for resetting a latch with one or more pull up transistors comprising one or more operatively non-functional high-k metal gate transistors connecting the internal node to the pull up reference voltage.
10. The method of claim 1 , where the security circuit comprises a timing delay circuit connecting an internal node to a reference voltage with one or more operatively non-functional high-k metal gate transistors connected as capacitors between the internal node and the reference voltage.
11. The method of claim 1 , further comprising reverse engineering the security circuit in the integrated circuit device to identify an extracted security circuit which provides the second electrical function that would disrupt a counterfeited integrated circuit device manufactured with the extracted security circuit.
12. The method of claim 2 , where selectively removing the plurality of sacrificial transistor gate structures comprises removing a high-k gate dielectric layer to form the plurality of gate electrode openings in the dielectric layer.
13. The method of claim 12 , further comprising firming a high-k gate dielectric layer in the plurality of gate electrode openings prior to selectively forming first and second work function metal layers in the plurality of gate electrode openings.
14. The method of claim 2 , where selectively removing the plurality of sacrificial transistor gate structures comprises removing one or more sacrificial polysilicon layers to form the plurality of gate electrode openings in the dielectric layer which expose a high-k gate dielectric layer.