Granted Patent B2

US 8,883,535 · App. 13/781,391 · Granted Nov 11, 2014

Abstract

Claims (47)

1. A method of fabricating a Microelectromechanical Systems (“MEMS”) device, comprising:

forming an interconnect layer and an underlying dielectric layer on a substrate, the interconnect layer patterned to include at least one interconnect line;

depositing a sacrificial layer over the interconnect layer;

patterning the sacrificial layer to form a contact opening therein through which a portion of the interconnect line is exposed;

forming a via opening extending through the sacrificial layer and into the substrate over which the sacrificial layer has been formed;

depositing a body of electrically-conductive material over the sacrificial layer, into the contact opening, and into the via opening to simultaneously produce an unpatterned transducer layer, a contact integrally formed with the unpatterned transducer layer, and a via integrally formed with the unpatterned transducer layer, the unpatterned transducer layer electrically coupled to the interconnect line through the contact;

patterning the unpatterned transducer layer to define, at least in part, a primary transducer structure having at least one movable component;

removing at least a portion of the sacrificial layer to release the movable component of the primary transducer structure;

thinning the substrate to reveal the via through a bottom surface of the substrate; and

producing a backside conductor over the bottom surface of the substrate and electrically coupled to the via.

2. The method of claim 1 wherein depositing the body of electrically-conductive material comprises depositing a layer of polycrystalline silicon over the sacrificial layer, into the contact opening, and into the via opening.

3. The method of claim 1 further comprising forming a via dielectric liner over one or more interior surfaces of the substrate defining the via opening prior to depositing the body of electrically-conductive material over the sacrificial layer.

4. The method of claim 1 further comprising:

forming an oxidation mask layer over an upper surface of the sacrificial layer and over the portion of the interconnect line exposed through the contact opening.

5. The method of claim 4 wherein the via opening is formed to extend through the oxidation mask layer, through the sacrificial layer, and into the substrate.

6. The method of claim 1 further comprising growing an oxide liner over one or more interior surfaces of the substrate defining the via opening prior to depositing the body of electrically-conductive material over the sacrificial layer.

7. The method of claim 1 further comprising attaching a MEMS cap over the primary transducer structure.

8. The method of claim 7 wherein thinning the substrate comprises grinding a backside of the substrate after attachment of the MEMS cap to impart the substrate with a predetermined thickness.

9. The method of claim 7 wherein removing comprises removing a central portion of the sacrificial layer to release the at least one movable component of the primary transducer structure, while leaving intact a peripheral portion of the sacrificial layer cooperating with the patterned transducer layer and the MEMS cap to hermetically enclose an interior of the MEMS device.

10. The method of claim 1 further comprising forming at least one embedded lithographical alignment feature extending into the substrate and visible through a backside of the substrate after thinning of the substrate.

11. The method of claim 10 wherein forming the at least one embedded lithographical alignment feature comprises:

forming an alignment feature opening extending through the sacrificial layer and into the substrate; and

depositing a fill material into the alignment feature opening to produce the embedded lithographical alignment feature within the substrate;

wherein the embedded lithographical alignment feature is revealed through the bottom surface of the substrate along with the via after thinning of the substrate.

12. The method of claim 11 wherein the fill material comprises polycrystalline silicon, and wherein the alignment feature opening is filled, at least in substantial part, during deposition of the body of electrically-conductive material over the sacrificial layer and into the via opening.

13. The method of claim 1 wherein the backside conductor comprises a backside bond pad, and wherein the method further comprises forming at least one backside interconnect line over a backside of the substrate, the at least one backside interconnect line electrically coupling the backside bond pad to the via.

14. The method of claim 1 further comprising packaging the MEMS device utilizing a chip scale package after producing the backside conductor on a backside of the substrate and electrically coupled to the via.

15. A method of fabricating a Microelectromechanical Systems (“MEMS”) device, comprising:

depositing a sacrificial layer over an interconnect line formed on a substrate;

patterning the sacrificial layer to form a contact opening through which a portion of the interconnect line is exposed;

etching a via opening extending through the sacrificial layer and into the substrate from an upper surface of the substrate;

depositing a body of polycrystalline silicon over the sacrificial layer, into the contact opening, and into the via opening to simultaneously produce an unpatterned transducer layer, a contact integrally formed with the unpatterned transducer layer, and a via integrally formed with the unpatterned transducer layer, the unpatterned transducer layer electrically coupled to the interconnect line through the contact;

patterning the unpatterned transducer layer to define, at least in part, a primary transducer structure;

attaching a MEMS cap over the primary transducer structure;

grinding a backside of the substrate to produce a ground backside through which the via is exposed;

producing a backside bond pad and a backside interconnect line on the ground backside of the substrate, the backside bond pad electrically coupled to the via by the backside interconnect line; and

forming at least one embedded lithographical alignment feature extending into the substrate from the upper surface of the substrate, located in a kerf area, and visible through the ground backside of the substrate.

16. A method of fabricating a Microelectromechanical Systems (“MEMS”) device, comprising:

providing a dielectric layer overlying a substrate, an interconnect line overlying the dielectric layer, and a sacrificial layer overlying the interconnect line;

patterning the sacrificial layer to form a contact opening through which a portion of the interconnect line is exposed;

forming an oxidation mask layer over the sacrificial layer and over the portion of the interconnect line exposed through the contact opening;

after forming the oxidation mask layer, forming a via opening extending through the sacrificial layer, through the oxidation mask layer, and into the substrate;

removing the oxidation mask layer;

after removing the oxidation mask layer, depositing a body of electrically-conductive material over the sacrificial layer, into the contact opening, and into the via opening to simultaneously produce an unpatterned transducer layer, a contact, and a via, respectively, wherein the via is in ohmic contact with the unpatterned transducer layer, and wherein the unpatterned transducer layer is electrically coupled to the interconnect line through the contact;

patterning the unpatterned transducer layer to define, at least in part, a primary transducer structure having at least one movable component;

removing at least a portion of the sacrificial layer to release the movable component of the primary transducer structure; and

revealing the via through a bottom surface of the substrate.

Assignments (21)