IP Library Granted Patent US 9,176,916
Granted Patent B2
US 9,176,916 · App. 13/775,313 · Granted Nov 3, 2015

Methods and systems for address mapping between host and expansion devices within system-in-package (SiP) solutions

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Quick Facts
Patent No.
US 9,176,916
App. No.
13/775,313
Granted
Nov 3, 2015
Kind
B2
Abstract

Methods and systems are disclosed for address mapping between die-to-die-port (DTDP) host devices and DTDP expansion devices for combined system-in-package (SiP) solutions. Interconnect circuitry having a plurality of ports is configured to provide communication from the host device to the expansion device so that the expansion device appears to be resident on the host device. Configurable address mapping is used to re-configure the host memory map to include expansion memory map details in a seamless fashion. Further, direct circuit interconnection blocks (e.g., using copper pillar (CuP) connectors) can be used to improve connectivity and performance.

Claims (38)

1. A die-to-die port (DTDP) system having plug-and-play connectivity, comprising:

a DTDP host device within a first integrated circuit; and

a DTDP expansion device within a second integrated circuit;

the DTDP host device within the first integrated circuit, comprising:

port interconnect circuitry having a plurality of ports and decode circuitry, the decode circuitry being configured to direct communications between the plurality of ports based upon a host address map; and

a circuit interconnection block coupled to the port interconnect circuitry and being configured to provide interconnectivity to the DTDP expansion device using at least one of the plurality of ports; and

the DTDP expansion device within the second integrated circuit, comprising:

an expansion circuit block configured to provide expansion functionality for the DTDP host device; and

a circuit interconnection block coupled to the port interconnect circuitry and being configured to provide interconnectivity to the DTDP host device;

wherein the DTDP expansion device is further configured to provide expansion device information to the DTDP host device during start-up or reset; and

wherein the DTDP host device is further configured to re-configure the host address map based upon the expansion device information so that the decode circuitry is configured to provide communications to the DTDP expansion device as if the DTDP expansion device were resident on the DTDP host device.

2. The DTDP system of claim 1 , wherein the first integrated circuit and the second integrated circuit are packaged within a single package to form a system-in-package (SiP) device.

3. The DTDP system of claim 1 , wherein the circuit interconnection block for the DTDP host device and the circuit interconnection block for the DTDP expansion device comprise copper pillar connectors.

4. The DTDP system of claim 1 , wherein the expansion device information provided by the DTDP expansion device comprises base address information.

5. The DTDP system of claim 4 , wherein the DTDP host device is configured to override a default address within the host address map using the base address information to form a re-configured base address.

6. The DTDP system of claim 5 , wherein the DTDP host device is further configured to translate an address for the DTDP expansion device based upon the re-configured base address.

7. The DTDP system of claim 1 , wherein the expansion device information provided by the DTDP expansion device comprises block size information.

8. The DTDP system of claim 7 , wherein the DTDP host device is configured to determine a base address for the DTDP expansion device using the block size information, to use the base address for the host address map, and to provide the base address to the DTDP expansion device.

9. The DTDP system of claim 1 , wherein the DTDP host device is configured to detect a presence of the DTDP expansion device at start-up or reset.

10. The DTDP system of claim 1 , wherein the DTDP expansion device comprises an expansion memory device or an expansion peripheral device.

11. The DTDP system of claim 1 , wherein the DTDP host device comprises a microcontroller.

12. A method for providing plug-and-play connectivity for a die-to-die port (DTDP) system, comprising:

providing connectivity between a plurality of ports using port interconnect circuitry within a DTDP host device within a first integrated circuit;

using decode circuitry for the port interconnect circuitry to direct communications within the port interconnect circuitry based upon a host address map;

utilizing a circuit interconnection block within the DTDP host device to provide interconnectivity to a DTDP expansion device using at least one of the plurality of ports;

utilizing a circuit interconnection block within the DTDP expansion device to provide interconnectivity to the DTDP host device, the DTDP expansion device being within a second integrated circuit;

communicating expansion device information from the DTDP expansion device to the DTDP host device during start-up or reset; and

re-configuring the host address map based upon the expansion device information so that the decode circuitry communicates with the DTDP expansion device as if the DTDP expansion device were resident on the DTDP host device.

13. The method of claim 12 , wherein the first integrated circuit and the second integrated circuit are packaged within a single package to form a system-in-package (SiP) device.

14. The method of claim 12 , further comprising utilizing copper pillar connectors for the circuit interconnection blocks for the DTDP host device and the DTDP expansion device.

15. The method of claim 12 , wherein the communicating step comprises communicating base address information for the DTDP expansion device.

16. The method of claim 15 , further comprising overriding a default address within the host address map using the base address information to form a re-configured base address.

17. The method of claim 16 , further comprising translating an address for the DTDP expansion device based upon the re-configured base address.

18. The method of claim 12 , wherein the communicating step comprises communicating block size information for the DTDP expansion device.

19. The method of claim 18 , further comprising determining a base address for the DTDP expansion device using the block size information, using the base address for the host address map, and providing the base address to the DTDP expansion device.

20. The method of claim 12 , further comprising using the DTDP host device to detect a presence of the DTDP expansion device at start-up or reset.

21. The method of claim 12 , wherein the DTDP expansion device comprises an expansion memory device or an expansion peripheral device.

22. The method of claim 12 , wherein the DTDP host device comprises a microcontroller.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2013
From: MILLER, GARY L.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029864/0800 →