APPARATUS AND METHOD FOR REDUCING PROCESSOR LATENCY
There is provided a data processing system comprising a central processing unit, a processor cache memory operably coupled to the central processing unit and an external connection operably coupled to the central processing unit and processor cache memory in which a portion of the data processing system is arranged to load data directly from the external connection into the processor cache memory and modify a source address of said directly loaded data. There is also provided a method of improving latency in a data processing system having a central processing unit operably coupled to a processor cache memory and an external connection operably coupled to the central processing unit and processor cache memory, comprising loading data directly from the external connection into the processor cache memory and modifying a source address for said data to become indicative of a location other than from the external connection.
1 . A data processing system comprising:
a central processing unit;
a processor cache memory operably coupled to the central processing unit; and
an external connection operably coupled to the central processing unit and processor cache memory, wherein a portion of the data processing system is arranged to:
load data directly from the external connection into the processor cache memory, and
modify a source address of said directly loaded data.
2 . The data processing system of claim 1 further comprising:
a main external system memory, wherein and the portion of the data processing system is further arranged to modify the source address to point towards a portion of main external system memory.
3 . The data processing system of claim 1 , wherein the portion of the data processing system is further arranged to set a dirty bit for the directly loaded data.
4 . The data processing system of claim 2 , wherein the portion of the data processing system is further arranged to notify the main external system memory of a portion of data storage in the main external system memory to be reserved for storing the directly loaded data after use.
5 . The data processing system of claim 1 , wherein the processor cache memory is level 2 cache memory.
6 . The data processing system of claim 1 , wherein the portion of the data processing system comprises a cache controller.
7 . The data processing system of claim 1 , further comprising:
a cache controller, wherein
the portion of the data processing system comprises a modified DMA module or an intermediate block.
8 . The data processing system of claim 7 , wherein the modified DMA controller or intermediate block is operably coupled to the cache controller through a proprietary connection or a dedicated master core connection.
9 . The data processing system of claim 1 , wherein the external connection comprises a USB connection.
10 . A method of improving latency in a data processing system, the method comprising:
loading data directly from an external connection into a processor cache memory coupled to the external connection; and
modifying, by a central processing unit coupled to the external connection and processor cache memory, a source address for said data to become indicative of a location other than from the external connection.
11 . The method of claim 10 further comprising:
modifying the source address for said data to become indicative of a location in a main external system memory coupled to the central processing unit.
12 . The method of claim 10 , further comprising setting a dirty bit for all data directly loaded into the processor cache memory.
13 . The method of claim 11 , further comprising notifying the main external system memory of a portion of data storage in the main external system memory to be reserved for storing the directly loaded data after use.
14 . The method of claim 10 , wherein the steps of modifying and notifying occur simultaneously with the loading of the data into the processor cache memory.
15 . The data processing system of claim 3 , wherein the portion of the data processing system is further arranged to notify the main external system memory of a portion of data storage in the main external system memory to be reserved for storing the directly loaded data after use.
16 . The data processing system claim 2 , further comprising:
a cache controller, wherein
the portion of the data processing system comprises a modified DMA module or an intermediate block.
17 . The method of claim 11 , further comprising setting a dirty bit for all data directly loaded into the processor cache memory.
18 . The method of claim 12 , further comprising notifying the main external system memory of a portion of data storage in the main external system memory to be reserved for storing the directly loaded data after use.