Integrating formation of a replacement gate transistor and a non-volatile memory cell having thin film storage
View Patent ↗A thermal oxide is formed in an NVM region and a logic region. A polysilicon layer is formed over the thermal oxide and patterned to form a dummy gate and a select gate in the logic and NVM regions, respectively. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, forming an opening. A second dielectric layer is formed over the select gate and within the opening, and a gate layer is formed over the second dielectric layer and within the opening, wherein the gate layer within the opening forms a logic gate and the gate layer is patterned to form a control gate in the NVM region.
1. A method for forming a semiconductor device having a non-volatile memory (NVM) region and a logic region, the method comprising:
forming a thermally grown oxygen-containing layer over a semiconductor layer in the NVM region and the logic region;
forming a polysilicon layer over the thermally grown oxygen-containing layer;
patterning the polysilicon layer and thermally grown oxygen-containing layer in the logic region to form a dummy gate and dummy gate dielectric in the logic region;
patterning the polysilicon layer and thermally grown oxygen-containing layer to form a select gate and a gate dielectric in the NVM region;
forming a first dielectric layer over the semiconductor layer in the NVM region and the logic region, wherein the first dielectric layer surrounds the select gate and gate dielectric in the NVM region and surrounds the dummy gate and dummy gate dielectric in the logic region;
removing the first dielectric layer from the NVM region while protecting the first dielectric layer in the logic region;
forming a charge storage layer over the semiconductor layer and select gate in the NVM region, and over the first dielectric layer and the dummy gate in the logic region;
removing the charge storage layer from the logic region;
removing the dummy gate and dummy gate dielectric in the logic region which results in an opening in the logic region;
forming a second dielectric layer over the charge storage layer in the NVM region and over the first dielectric layer and within the opening in the logic region;
forming a gate layer over the second dielectric layer in the NVM region and over the second dielectric layer and in the opening in the logic region;
removing a top portion of the gate layer in the NVM region and the logic region, wherein a remaining portion of the gate layer in the opening forms a logic gate in the logic region; and
patterning a remaining portion of the gate layer in the NVM region to form a control gate in the NVM region that is laterally adjacent the select gate, wherein a top surface of the control gate is substantially coplanar with a top surface of the logic gate.
2. The method of claim 1 , wherein the step of patterning the remaining portion of the gate layer in the NVM region is further characterized in that a top surface of the select gate is substantially coplanar with the top surface of the control gate.
3. The method of claim 1 , wherein the step of forming the first dielectric layer is performed such that a top surface of the first dielectric layer is substantially coplanar with top surfaces of the select gate and the dummy gate.
4. The method of claim 3 , further comprising:
after the step of forming the first dielectric layer and prior to the step of forming the charge storage layer, removing a top portion of the select gate such that the top surface of the select gate is recessed from the top surface of the first dielectric layer.
5. The method of claim 4 , wherein the step of patterning the remaining portion of the gate layer in the NVM region is further characterized in that the control gate is laterally adjacent the select gate and overlaps one sidewall of the select gate.
6. The method of claim 3 , wherein the step of forming the first dielectric layer comprises:
forming the first dielectric layer over the semiconductor layer, the select gate, and the dummy gate; and
planarizing the first dielectric layer to expose the select gate and the dummy gate.
7. The method of claim 1 , wherein the step of forming the second dielectric layer is performed such that the second dielectric layer is in contact with the semiconductor layer within the opening in the logic region.
8. The method of claim 1 , wherein the second dielectric layer comprises a dielectric material having a high dielectric constant.
9. The method of claim 8 , wherein the step of forming the charge storage layer comprises:
forming a third dielectric layer;
forming nanocrystals on the third dielectric layer; and
forming a fill dielectric over the nanocrystals such that the fill dielectric extends above the nanocrystals.
10. The method of claim 9 , wherein the second dielectric layer is further characterized as a portion of the charge storage layer.
11. The method of claim 8 , wherein the step of forming the charge storage layer comprises:
forming a third dielectric layer;
forming a silicon nitride storage layer over the third dielectric layer; and
forming a fill dielectric over the silicon nitride storage layer.
12. The method of claim 8 , wherein the gate layer comprises a metal.
13. The method of claim 1 , further comprising:
forming a sidewall spacer adjacent a sidewall of the dummy gate; and
forming source/drain regions in the semiconductor layer adjacent the dummy gate.
14. A method for forming a semiconductor device having a non-volatile memory (NVM) region and a logic region, the method comprising:
forming a thermally grown oxygen-containing layer over a semiconductor layer in the NVM region and the logic region;
forming a polysilicon layer over the thermally grown oxygen-containing layer;
patterning the polysilicon layer and the thermally grown oxygen-containing layer in the logic region to form a dummy gate and dummy gate dielectric in the logic region;
patterning the polysilicon layer and thermally grown oxygen-containing layer to form a select gate and a gate dielectric in the NVM region;
forming a first dielectric layer over the semiconductor layer in the NVM region and the logic region, wherein the first dielectric layer surrounds the select gate and gate dielectric in the NVM region and surrounds the dummy gate and dummy gate dielectric in the logic region, and wherein a top surface of the first dielectric layer is substantially coplanar with top surfaces of the select gate and the dummy gate;
removing a portion of the select gate such that the top surface of the select gate is recessed from the top surface of the first dielectric layer;
after the step of removing the portion of the select gate, removing the first dielectric layer from the NVM region while protecting the first dielectric layer in the logic region;
forming a charge storage layer over the semiconductor layer and the select gate in the NVM region, and over the first dielectric layer and the dummy gate in the logic region;
removing the charge storage layer from the logic region;
removing the dummy gate and dummy gate dielectric in the logic region which results in an opening in the logic region;
forming a second dielectric layer over the charge storage layer in the NVM region and over the first dielectric layer and within the opening in the logic region;
forming a gate layer over the second dielectric layer in the NVM region and over the second dielectric layer and in the opening in the logic region;
removing a top portion of the gate layer in the NVM region and the logic region, wherein a remaining portion of the gate layer in the opening forms a logic gate in the logic region; and
patterning a remaining portion of the gate layer in the NVM region to form a control gate in the NVM region that is laterally adjacent the select gate and overlaps one sidewall of the select gate.
15. The method of claim 14 , wherein the second dielectric layer comprises a dielectric material having a high dielectric constant.
16. The method of claim 14 , wherein the gate layer comprises a metal.
17. The method of claim 14 , wherein the charge storage layer comprises one of nanocrystals or silicon nitride.
18. A method for forming a semiconductor device having a non-volatile memory (NVM) region and a logic region, the method comprising:
forming a thermally grown oxygen-containing layer over a semiconductor layer in the NVM region and the logic region;
forming a polysilicon layer over the thermally grown oxygen-containing layer;
patterning the polysilicon layer and thermally grown oxygen-containing layer in the logic region to form a dummy gate and dummy gate dielectric in the logic region;
patterning the polysilicon layer and thermally grown oxygen-containing layer to form a select gate and a gate dielectric in the NVM region;
forming a first dielectric layer over the semiconductor layer, the select gate, and the dummy gate;
planarizing the first dielectric layer to expose the select gate and the dummy gate;
removing the first dielectric layer from the NVM region while protecting the first dielectric layer in the logic region;
forming a charge storage layer over the semiconductor layer and select gate in the NVM region, and over the first dielectric layer and the dummy gate in the logic region;
removing the charge storage layer from the logic region;
removing the dummy gate and dummy gate dielectric in the logic region which results in an opening in the logic region;
forming a second dielectric layer over the charge storage layer in the NVM region and over the first dielectric layer and within the opening in the logic region, wherein the second dielectric layer comprises a dielectric material having a high dielectric constant;
forming a metal-containing gate layer over the second dielectric layer in the NVM region and over the second dielectric layer and in the opening in the logic region;
planarizing the metal-containing gate layer in the NVM region and the logic region to expose the first dielectric layer in the logic region, wherein a remaining portion of the metal-containing gate layer in the opening forms a logic gate in the logic region; and
after planarizing the metal-containing gate layer, patterning the metal-containing gate layer in the NVM region to form a control gate in the NVM region that is laterally adjacent the select gate, wherein a top surface of the control gate is substantially coplanar with a top surface of the logic gate.
19. The method of claim 18 , wherein the step of patterning the metal-containing gate layer in the NVM region is further characterized in that a top surface of the select gate is substantially coplanar with the top surface of the control gate.
20. The method of claim 18 , further comprising:
after the step of forming the first dielectric layer and prior to the step of forming the charge storage layer, removing a top portion of the select gate such that the top surface of the select gate is recessed from the top surface of the first dielectric layer,
wherein the step of patterning the remaining portion of the gate layer in the NVM region is further characterized in that the control gate is laterally adjacent the select gate and overlaps one sidewall of the select gate.