IP Library Granted Patent US 8,921,203
Granted Patent B2
US 8,921,203 · App. 13/750,419 · Granted Dec 30, 2014

Method of forming an integrated circuit having varying substrate depth

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Quick Facts
Patent No.
US 8,921,203
App. No.
13/750,419
Granted
Dec 30, 2014
Kind
B2
Abstract

A method for forming a semiconductor device includes providing a substrate having a first major surface and a second major surface, removing a first portion of the substrate to form a cavity at the first major surface of the substrate, bonding the first major surface of the substrate to a carrier substrate after forming the cavity, and reducing a thickness of the substrate. The method further includes forming a first accelerometer device at the second major surface such that at least a portion of the first accelerometer device is over the cavity and forming a second accelerometer device at the second major surface such that the second accelerometer device is not disposed over the cavity.

Claims (27)

1. A method, comprising:

providing a substrate having a first major surface and a second major surface;

removing a first portion of the substrate to form a cavity at the first major surface of the substrate;

bonding the first major surface of the substrate to a carrier substrate after forming the cavity;

reducing a thickness of the substrate such that the substrate has a first thickness between the second major surface and a bottom of the cavity and a second thickness between the first major surface and the second major surface after the thickness is reduced, the first thickness less than the second thickness;

forming a first accelerometer device at the second major surface such that at least a portion of the first accelerometer device is over the cavity; and

forming a second accelerometer device at the second major surface such that the second accelerometer device is not disposed over the cavity.

2. The method of claim 1 , wherein the first thickness is less than 65 percent of the second thickness.

3. The method of claim 1 , wherein the first thickness is less than 60 percent of the second thickness.

4. The method of claim 1 , wherein the first thickness is less than 25 percent of the second thickness.

5. The method of claim 1 , wherein the portion of the first accelerometer device comprises an accelerometer spring.

6. The method of claim 1 , wherein the second accelerometer device comprises an accelerometer spring.

7. The method of claim 1 , wherein reducing the thickness comprises grinding the semiconductor substrate.

8. The method of claim 1 , further comprising forming a polysilicon layer over a portion of the first major surface prior to bonding the first side to the carrier substrate.

9. The method of claim 8 , further comprising depositing a dielectric layer over the polysilicon layer.

10. The method of claim 1 , wherein the first accelerometer device is associated with a first direction and wherein the second accelerometer device is associated with a second direction different from the first direction.

11. The method of claim 10 , further comprising forming a third accelerometer device at the second major surface such that at least a portion of the third accelerometer is not disposed over the bottom of the cavity.

12. The method of claim 11 , wherein the portion of the third accelerometer device comprises an accelerometer spring.

13. The method of claim 11 , wherein the third accelerometer device is associated with a third direction different from the first and second directions.

14. A method, comprising:

bonding a first major surface of a substrate to a carrier substrate, the substrate having the first major surface and a second major surface, the substrate including a cavity at the first major surface;

removing material from the second major surface of the substrate such that the substrate has a first thickness between the second major surface and a bottom of the cavity and a second thickness between the first major surface and the second major surface after the material is removed, the first thickness less than the second thickness;

forming a first accelerometer device from the second major surface such that an accelerometer spring of the first accelerometer device is over the cavity; and

forming a second accelerometer device and a third accelerometer device from the second major surface such that the second accelerometer device and the third accelerometer device are not disposed over the cavity, the first, second and third accelerometer devices associated with different directions of three directions.

15. The method of claim 14 , wherein the first thickness is less than 65 percent of the second thickness.

16. The method of claim 14 , wherein removing the material comprises grinding the semiconductor substrate.

17. The method of claim 14 , further comprising forming a polysilicon layer over a portion of the first major surface prior to bonding the first side to the carrier substrate.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2013
From: KARLIN, LISA H.; DESAI, HEMANT D.; JIA, KEMIAO
To: FREESCALE SEMICONDUCTOR, INC.
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