IP Library Granted Patent US 8,766,703
Granted Patent B1
US 8,766,703 · App. 13/835,690 · Granted Jul 1, 2014

Method and apparatus for sensing on-chip characteristics

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Quick Facts
Patent No.
US 8,766,703
App. No.
13/835,690
Granted
Jul 1, 2014
Kind
B1
Abstract

A sensor circuit performs a method for sensing on-chip characteristics. The method includes generating a first voltage using a drive current through a first set of transistors that are operating in saturation mode and generating a second voltage using subthreshold leakage current from a second set of transistors that are in subthreshold mode. The method further includes comparing the second voltage to the first voltage to sense an on-chip characteristic. The sensed on-chip characteristic can be temperature and/or gate length variation.

Claims (39)

1. A method performed by a sensor circuit on an integrated circuit chip for sensing on-chip characteristics, the method comprising:

generating a first voltage using a drive current through a first set of transistors that are operating in saturation mode;

generating a second voltage using subthreshold leakage current from a second set of transistors that are in subthreshold mode;

comparing the second voltage to the first voltage to sense an on-chip characteristic.

2. The method of claim 1 , wherein comparing the second voltage to the first voltage to sense the on-chip characteristic comprises:

sensing a voltage difference between the first and second voltages; and

amplifying the voltage difference to generate a digital output signal that is representative of the sensed on-chip characteristic.

3. The method of claim 2 further comprising providing the digital output signal to an adjustment circuit to compensate for the sensed on-chip characteristic.

4. The method of claim 1 , wherein the sensed on-chip characteristic comprises temperature.

5. The method of claim 1 , wherein the sensed on-chip characteristic comprises gate length variation.

6. The method of claim 1 , wherein generating the first voltage using the drive current through the first set of transistors comprises generating the first voltage using the first set of transistors configured with a first gate length, wherein generating the second voltage using the subthreshold leakage current through the second set of transistors comprises generating the second voltage using the second set of transistors configured with a gate length that is shorter than the gate length of the first set of transistors.

7. The method of claim 1 further comprising generating the second voltage using a current through a third set of transistors that are operating in triode mode or saturation mode.

8. The method of claim 1 further comprising:

receiving an enable signal and responsively activating the sensor circuit to perform the method;

receiving a disable signal and responsively deactivating the sensor circuit to prevent performance of the method.

9. The method of claim 8 , wherein the enable and disable signals are received into at least one transistor within or coupled to the first set of transistors.

10. The method of claim 8 , wherein the enable signal is received into a power-gating transistor, connected to the sensor circuit, to provide a power supply voltage to activate the sensor circuit, and the disable signal is received into the power-gating transistor to remove the power supply voltage to deactivate the sensor circuit.

11. A sensor circuit configured for sensing on-chip characteristics, the sensor circuit comprising:

a first set of transistors configured to generate a first voltage when operating in saturation mode;

a second set of transistors coupled to the first set of transistors, wherein the second set of transistors is configured to contribute to the generation of a second voltage, which indicates an on-chip characteristic, when each transistor in the second set is in subthreshold mode;

a sense amplifier circuit coupled to the first and second sets of transistors and configured to detect a difference between the first and second voltages to sense the on-chip characteristic.

12. The sensor circuit of claim 11 , wherein the first set of transistors is configured with at least one transistor characteristic, and wherein the second set of transistors is configured differently from the first set of transistors with regard to the at least one transistor characteristic, which contributes to the generation of the second voltage, and which indicates the on-chip characteristic.

13. The sensor circuit of claim 12 , wherein the at least one transistor characteristic comprises gate length, and each transistor in the first set of transistors is configured to have a longer gate length than a gate length of each transistor in the second set of transistors.

14. The sensor circuit of claim 12 , wherein the at least one transistor characteristic comprises voltage threshold, and each transistor in the first set of transistors is configured to have a higher voltage threshold than a voltage threshold of each transistor in the second set of transistors.

15. The sensor circuit of claim 13 further comprising a third set of transistors coupled to the first and second sets of transistors, wherein the third set of transistors in configured to contribute to the generation of the second voltage when the transistors in the third set are operating in triode mode or in saturation mode.

16. The sensor circuit of claim 15 further comprising a control input coupled to at least the first set of transistors, wherein the control input is configured to provide an enable signal to enable at least one current path in the sensor circuit and a disable signal to block at least one current path in the sensor circuit.

17. The sensor circuit of claim 16 , wherein the control input comprises at least one of:

an input node coupled to at least one transistor in the first set transistors; or

a metal-oxide semiconductor field effect transistor coupled to at least one power supply source configured to supply a power supply voltage for the first, second, and third sets of transistors.

18. The sensor circuit of claim 11 , wherein the sense amplifier circuit comprises a third set of transistors configured to:

detect a voltage difference between the first and second voltages; and

amplify the voltage difference to generate a digital output signal that is representative of the sensed on-chip characteristic.

19. A system comprising:

an integrated circuit chip;

a set of sensor circuits disposed on the integrated circuit chip, each sensor circuit comprising:

a first set of transistors configured with at least one transistor characteristic and configured to generate a first voltage when operating in saturation mode;

a second set of transistors coupled to the first set of transistors, wherein the second set of transistors is configured to generate a second voltage, which indicates an on-chip characteristic, when a first subset of the second set of transistors is in subthreshold mode and is configured differently from the first set of transistors with regard to the at least one transistor characteristic and when a second subset of the second set of transistors is operating in triode mode or saturation mode;

a sense amplifier circuit coupled to the first and second sets of transistors, wherein the sense amplifier circuit is configured to sense a voltage difference between the first and second voltages and amplify the voltage difference to generate a digital output signal that is representative of the on-chip characteristic.

20. The system of claim 19 , wherein the integrated circuit chip has a first circuit block separated from a second circuit block, and the set of sensor circuits comprises a first sensor circuit disposed on the first circuit block and a second sensor circuit disposed on the second circuit block, wherein the first sensor circuit is configured to sense at least one of temperature or line variation on the first circuit block, and the second sensor circuit is configured to sense at least one of temperature or line variation on the second circuit block.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2013
From: BURNETT, JAMES D.
To: FREESCALE SEMICONDUCTOR INC.
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