Electronic circuit and method for state retention power gating
View Patent ↗An electronic circuit includes a processor having a functional mode and a low power mode, said processor comprising state flip-flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode; a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power from the processor when the processor is in the low power mode; a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to identify the non-reset flip-flops and to generate non-reset information that identifies the non-reset flip-flops; and a recovery circuit, coupled to a memory module and to the state flip-flops.
1. An electronic circuit, comprising:
a processor having a functional mode and a low power mode, said processor comprising state flip-flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode, wherein the state flip-flops are arranged in scan chains;
a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power to the processor when the processor is in the low power mode;
a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to determine that a scan chain is a non-reset scan chain in response to the scan chain including a non-reset flip-flop, to generate non-reset information that identifies the non-reset flip-flops, and to generate additional non-reset information including a value of each flip-flop in the scan chain in response to determining that the scan chain is a non-reset scan chain; and
a recovery circuit, coupled to a memory module and to the state flip-flops, said recovery circuit is arranged to retrieve the non-reset information from the memory module when the processor exits the low power mode, and to provide the non-reset value only to the non-reset flip-flops that are identified by the non-reset information; and
wherein said memory module is arranged to store the non-reset information when the processor is in the low power mode.
2. The electronic circuit according to claim 1 , wherein the non-reset value identification module is arranged to generate non-reset information about locations of the non-reset flip-flops.
3. The electronic circuit according to claim 1 , wherein the processor further comprises additional scan chains; wherein a number of the multiple scan chains is a fraction of the additional chain scans.
4. The electronic circuit according to claim 1 , wherein a number of the state flip-flops is less than a half of a number of the additional flip-flops.
5. The electronic circuit according to claim 1 , wherein a number of the state flip-flops is less than one fifth of a number of the additional flip-flops.
6. The electronic circuit according to claim 1 , wherein the state flip-flops are grouped to scan chains based on a probability of the state flip-flops to be in a non-reset state.
7. A method for storing a state of a processor, the method comprising:
sending to a non-reset value identification module and to a recovery circuit, at least one control signal indicating whether a processor should exit a functional mode or exit a state retention mode; wherein said processor comprises state flip-flops and additional flip-flops;
when said at least one control signal indicates that the processor should exit the functional mode:
identifying, in response to a receiving of the at least one control signal by the non-reset value identification module, non-reset flip-flops; wherein each non-reset flip-flop is a state flip-flop that stores a non-reset value when the processor exits the functional mode;
generating non-reset information that identifies the non-reset flip-flops;
storing the non-reset information in a memory module;
determining that a scan chain is a non-reset scan chain in response to the scan, chain including a non-reset flip-flop;
generating additional non-reset information that identifies a value of each flip-flop in the scan chain in response to determining that the scan chain is a non-reset scan chain;
storing the additional non-reset information in the memory module; and
stopping a supply of power to the processor;
when said at least one control signal indicates that the processor should exit the low power mode:
providing power to the processor;
retrieving, in response to a receiving of the control signal by the recovery circuit, the non-reset information from the memory module;
providing the non-reset value only to non-reset flip-flops that are identified by the non-reset information;
allowing flip-flops that differ from the non-reset flip-flops to converge to a reset state; and
operating the processor in the functional mode.
8. The method according to claim 7 , wherein the method comprises generating, by the non-reset value identification module, non-reset information about locations of the non-reset flip-flops.
9. The method according to claim 7 , wherein the multiple scan chains are a fraction of chain scans included in the processor.
10. The method according to claim 7 , wherein a number of the state flip-flops is less than a half of a number of the additional flip-flops.
11. The method according to claim 7 , wherein a number of the state flip-flops is less than one fifth of a number of the additional flip-flops.
12. The method according to claim 7 , wherein the state flip-flops are grouped to scan chains based on a probability of the state flip-flops to be in a non-reset state.
13. A method for storing a state of a processor, the method comprising:
sending to a non-reset value identification module and to a recovery circuit, at least one control signal indicating whether a processor should exit a functional mode or exit a state retention mode; wherein said processor comprises state flip-flops and additional flip-flops; and
when said at least one control signal indicates that the processor should exit the functional mode:
identifying, in response to a receiving of the at least one control signal by the non-reset value identification module, non-reset flip-flops; wherein each non-reset flip-flop is a state flip-flop that stores a non-reset value when the processor exits the functional mode;
generating non-reset information that identifies the non-reset flip-flops;
storing the non-reset information in a memory module;
determining that a scan chain is a non-reset scan chain in response to the scan, chain including a non-reset flip-flop;
generating additional non-reset information that identifies a value of each flip-flop in the scan chain in response to determining that the scan chain is a non-reset scan chain;
storing the additional non-reset information in the memory module; and
stopping a supply of power to the processor.
14. The method of claim 13 , further comprising:
generating, by the non-reset value identification module, non-reset information about locations of the non-reset flip-flops.
15. The method of claim 13 , wherein the multiple scan chains are a fraction of chain scans included in the processor.
16. The method of claim 13 , wherein a number of the state flip-flops is less than a half of a number of the additional flip-flops.
17. The method of claim 13 , wherein a number of the state flip-flops is less than one fifth of a number of the additional flip-flops.
18. The method of claim 13 , wherein the state flip-flops are grouped to chain scans based on a probability of the state flip-flops to be in a non-reset state.