Methods and systems for pushing dirty linefill buffer contents to external bus upon linefill request failures
View Patent ↗Methods and systems are disclosed for recovering dirty linefill buffer data upon linefill request failures. When a linefill request failure occurs and the linefill buffer has been marked as dirty, such as due to a system bus failure, the contents of the linefill buffer are pushed back to the system bus. The dirty data within the linefill buffer can then be used to update the external memory. The disclosed embodiments are useful for a wide variety of applications, including those requiring low data failure rates.
1. A cache system, comprising:
a cache configured to store a plurality of cache lines;
a linefill buffer configured to store at least one cache line;
a load/store unit configured to store data within the linefill buffer during a linefill request for the cache, the stored data being received from a system bus; and
a cache controller configured to mark the stored data as dirty if updated within the linefill buffer during the linefill request and to push the dirty data from the linefill buffer to the system bus if the linefill request fails.
2. The cache system of claim 1 , wherein the linefill buffer is configured to store data in the form of a plurality of double-word bytes.
3. The cache system of claim 1 , wherein the linefill buffer is configured to have at least one write request bit that indicates whether data is to be written to the system bus upon a linefill request failure.
4. The cache system of claim 1 , wherein the cache system further comprises a bus interface unit configured to be coupled to a system bus, and wherein the cache controller is configured to push the dirty data from the linefill buffer to the system bus through the bus interface unit.
5. The cache system of claim 1 , wherein the cache system further comprises a bus interface unit configured to be coupled to a system bus and a store buffer configured to store data to be written to external memory, and wherein the cache controller is configured to push the dirty data from the linefill buffer to the system bus through the store buffer and the bus interface unit.
6. The cache system of claim 1 , wherein the cache controller is further configured to discard the data in the linefill buffer if the data is not marked as dirty and the linefill request fails.
7. The cache system of claim 1 , wherein the cache controller is configured to utilize a plurality of write requests to a bus interface controller to push the dirty data from the linefill buffer to the system bus.
8. The cache system of claim 1 , wherein the linefill buffer is configured to have at least one dirty bit that indicates whether data within the linefill buffer is dirty.
9. The cache system of claim 1 , wherein the dirty data pushed to the system bus is available for an update to a memory.
10. A processor system, comprising:
a processor coupled to a system bus;
a memory coupled to the system bus; and
a cache system coupled to the system bus and configured to store cache lines from the memory and to communicate cache lines to the processor through the system bus, the cache system comprising:
a cache configured to store a plurality of cache lines;
a linefill buffer configured to store at least one cache line; and
a load/store unit configured to store data within the linefill buffer during a linefill request for the cache system, the stored data being received from the system bus; and
a cache controller configured to mark the stored data as dirty if updated within the linefill buffer during the linefill request and to push the dirty data from the linefill buffer to the system bus if the linefill request fails.
11. The processor system of claim 10 , wherein the cache system further comprises a bus interface unit coupled to the system bus, and wherein the cache controller is configured to push the dirty data from the linefill buffer to the system bus through the bus interface unit.
12. The processor system of claim 10 , wherein the cache system further comprises a store buffer configured to be used to store data to be written to the memory, and wherein the cache controller is configured to push the dirty data from the linefill buffer to the system bus through the store buffer and the bus interface unit.
13. The processor system of claim 10 , wherein the linefill buffer is configured to have at least one dirty bit that indicates whether data within the linefill buffer is dirty and to have at least one write request bit that indicates whether data is to be written to the system bus upon a linefill request failure.
14. The processor system of claim 10 , wherein the dirty data pushed to the system bus is available for an update to the memory.
15. A method for recovering dirty linefill buffer data after linefill request failures, comprising:
receiving data from a system bus for a linefill request for a cache within a cache system;
storing the data within a linefill buffer during the linefill request;
marking the stored data as dirty if updated while within the linefill buffer; and
pushing the dirty data from the linefill buffer to the system bus if the linefill request fails.
16. The method of claim 15 , further comprising updating data within a main memory using the dirty data pushed to the system bus.
17. The method of claim 15 , further comprising setting at least one write request bit within the linefill buffer to indicate whether data is to be written to the system bus upon a linefill request failure.
18. The method of claim 15 , wherein the pushing step comprises pushing the dirty data from the linefill buffer through a bus interface unit to the system bus.
19. The method of claim 15 , wherein the pushing step comprises pushing the dirty data from the linefill buffer to a store buffer and from the store buffer through a bus interface unit to the system bus.
20. The method of claim 15 , further comprising discarding the data in the linefill buffer if the data is not marked as dirty and the linefill request fails.
21. The method of claim 15 , wherein the pushing step comprises utilizing a plurality of write requests to a bus interface controller to push the dirty data from the linefill buffer to the system bus.
22. The method of claim 15 , further comprising setting at least one bit in the linefill buffer to indicate whether data within the linefill buffer is dirty.