IP Library Granted Patent US 9,041,367
Granted Patent B2
US 9,041,367 · App. 13/828,213 · Granted May 26, 2015

Voltage regulator with current limiter

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Quick Facts
Patent No.
US 9,041,367
App. No.
13/828,213
Granted
May 26, 2015
Kind
B2
Abstract

A voltage regulator includes an amplifier having a first input coupled to a first reference voltage and a second input coupled to a voltage feedback signal; a multiplexer having a first input coupled to an output of the amplifier, a second input coupled to a voltage clamp signal, and a control input; and a control circuit having a first input coupled to an over current indicator, a second input coupled to a no over voltage indicator, a third input coupled to a timer signal, and an output coupled to the control input of the multiplexer.

Claims (48)

1. A voltage regulator comprising:

an amplifier having a first input coupled to a first reference voltage and a second input coupled to a voltage feedback signal;

a multiplexer having a first input coupled to an output of the amplifier, a second input coupled to a voltage clamp signal, and a control input, wherein when the control input selects the first input, the voltage regulator operates in a closed loop in which the voltage feedback signal is regulated and when the control input selects the second input, the voltage regulator operates in an open loop in which the voltage feedback signal is not regulated;

a control circuit having a first input coupled to an over current indicator, a second input coupled to a no over voltage indicator, a third input coupled to a timer signal, and an output coupled to the control input of the multiplexer.

2. The voltage regulator of claim 1 , further comprising:

a load circuit coupled to the second input of the amplifier.

3. The voltage regulator of claim 2 , further comprising:

a ballast transistor having a gate terminal coupled to an output of the multiplexer, a source terminal coupled to a supply voltage, and a drain terminal coupled to the load circuit and the second input of the amplifier.

4. The voltage regulator of claim 1 , further comprising:

a current scalar transistor having a gate terminal coupled to the output of the multiplexer, a source terminal coupled to a supply voltage, and a drain terminal coupled to an input of a first current to voltage converter circuit.

5. The voltage regulator of claim 4 , further comprising:

the first current to voltage converter circuit configured to provide a scaled current to an over current detection circuit, and

the over current detection circuit outputs the over current indicator.

6. The voltage regulator of claim 5 , further comprising:

a second current to voltage converter circuit having an input coupled to a maximum reference current supply and an output coupled to the over current detection circuit.

7. The voltage regulator of claim 6 , wherein the over current detection circuit ( 28 ) includes a comparator circuit.

8. The voltage regulator of claim 1 , further comprising:

an over voltage detection circuit having a first input coupled to a second reference voltage, a second input coupled to the voltage feedback signal, and an output that provides the no over voltage indicator.

9. The voltage regulator of claim 8 , wherein the over voltage detection circuit includes a comparator circuit.

10. The voltage regulator of claim 1 , further comprising:

an analog timer circuit configured to provide the timer signal, wherein current output by the voltage regulator is limited until the timer signal expires when an over current condition is detected and an over voltage condition is not detected.

11. A voltage regulator comprising:

a regulator control circuit having a first input coupled to an over current indicator, a second input couple to a no over voltage indicator, a third input coupled to a timer signal, and an output coupled to provide a control signal; and

a multiplexer having a first input coupled to an amplifier output signal, a second input coupled to a voltage limit signal, and a control input coupled to the control signal, wherein

the multiplexer outputs the amplifier output signal when

an over current condition does not exist and

an over voltage condition exists, and

the multiplexer outputs the voltage limit signal when

the over current condition exists and

the timer signal has not expired when the over voltage condition does not exist.

12. The voltage regulator of claim 11 , wherein the multiplexer outputs the amplifier output signal when the over voltage condition does not exist and the timer signal has expired.

13. The voltage regulator of claim 11 , further comprising:

an amplifier coupled to receive a reference voltage at a first input and a feedback voltage at a second input and to output the amplifier output signal, wherein the feedback voltage is based on a regulator supply voltage coupled to a load.

14. The voltage regulator of claim 13 , further comprising:

an over voltage detection circuit configured to compare a second reference voltage to the feedback voltage and to set a no over voltage indicator to indicate whether the over voltage condition exists.

15. The voltage regulator of claim 11 , further comprising:

an over current detection circuit configured to compare a scaled current to a maximum current and to set an over current indicator to indicate whether the over current condition exists.

16. The voltage regulator of claim 15 , further comprising:

an analog timer circuit coupled to receive the over current indicator and the no over voltage indicator and to output an unexpired timer signal for a selected amount of time.

17. The voltage regulator of claim 11 , further comprising:

a ballast transistor having a gate terminal coupled to an output of the multiplexer, a source terminal coupled to a supply voltage, and a drain terminal coupled to a load circuit.

18. The voltage regulator of claim 11 , further comprising:

a current scalar transistor having a gate terminal coupled to an output of the multiplexer, a source terminal coupled to a supply voltage, and a drain terminal coupled to an input of a first current to voltage converter circuit.

19. A method of regulating voltage, comprising:

monitoring a current of a load device; when the current required by the load device is greater than a maximum current: limiting the current supplied to the load device to a first predetermined current level being lower than or equal to the maximum current, and activating a timer; and

monitoring a voltage supplied to the load device; when the voltage supplied to the load device is less than or equal to a maximum voltage: waiting until the timer expires, and allowing the load device to draw a second predetermined current level being greater than the maximum current after the timer expires.

20. The method of claim 19 further comprising:

when voltage supplied to the load device is greater than the maximum voltage, supplying a regulated voltage to the load device.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CONFIRMATORY ASSIGNMENT Recorded Feb 28, 2018
From: DAO, CHRIS C.; PIETRI, STEFANO; REN, JUXIANG
To: NXP USA, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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From: DAO, CHRIS C.; PIETRI, STEFANO; REN, JUXIANG
To: FREESCALE SEMICONDUCTOR, INC.
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