Memory management unit for a microprocessor system, microprocessor system and method for managing memory
View Patent ↗The invention pertains to a memory management unit for a microprocessor system, the memory management unit being connected or connectable to at least one processor core of the microprocessor system and being connected or connectable to a physical memory of the microprocessor system. The memory management unit is adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware The memory management unit comprises a first register table indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other; a second register table indicating an allowed address range of physical addresses accessible to a process running in or under supervisor mode; wherein the memory management unit is adapted to prevent write access to the second register table by a process not in hypervisor mode. The memory management unit is further adapted to allow write access to the first register table of a process running in or under supervisor mode to reconfigure the physical address information indicated in the first register table with memory mapping information relating to at least one physical address, if the at least one physical address is in the allowed address range, and to prevent write access to the first register table of the process running in or under supervisor mode if the at least one physical address is not in the allowed address range. The invention also pertains to a microprocessor system and a method for managing memory.
1. A memory management unit for a microprocessor system, the memory management unit being connected to at least one processor core of the microprocessor system and being connected to a physical memory of the microprocessor system, the memory management unit being adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware, the memory management unit comprising:
a first register table indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other;
a second register table indicating an allowed address range of physical addresses accessible to a process running in or under the supervisor mode;
wherein the memory management unit is adapted to prevent write access to the second register table by a process not in the hypervisor mode; and
wherein the memory management unit is further adapted to allow write access to the first register table of a process running in or under the supervisor mode to reconfigure the physical address information indicated in the first register table with memory mapping information relating to at least one physical address, if the at least one physical address is in the allowed address range, and to prevent write access to the first register table of the process running in or under the supervisor mode if the at least one physical address is not in the allowed address range.
2. The memory management unit according to claim 1 , wherein the memory mapping information is stored in a configuration memory region indicated by the second register table, wherein data stored in the configuration memory region represents the allowed address range.
3. The memory management unit according to claim 2 , further comprising the process running in or under the supervisor mode being allowed to read the memory mapping information.
4. The memory management unit according to claim 1 , wherein the second register table is adapted to indicate allowed address ranges for two or more processes running in or under the supervisor mode.
5. The memory management unit according to claim 1 , wherein the memory management unit further comprises a third register table indicating virtual address information for mapping at least one virtual address and at least one physical address onto each other.
6. The memory management unit according to claim 5 , wherein the at least one physical address mapped onto at least one virtual address is an actual physical address.
7. The memory management unit according to claim 5 , wherein the memory management unit is adapted to allow write access to the third register table of a process running in or under the supervisor mode.
8. The memory management unit according to claim 1 , wherein the at least one actual physical address is an address of physical memory.
9. The memory management unit according to claim 1 , wherein the memory management unit is further adapted to allow write access to the first register table of a process running in the hypervisor mode.
10. A microprocessor system comprising at least one processor core and a memory management unit according to claim 1 , the memory management unit being connected to the processor core.
11. The microprocessor system according to claim 10 , the memory management unit being connected to a physical memory.
12. A method of memory management for a microprocessor system with a processor core, a physical memory and a memory management unit according to claim 1 , the memory management unit being connected to the processor core and the physical memory, wherein a request for write access to the first register table by a process running in or under the supervisor mode to reconfigure the physical address information in the first register table with memory mapping information relating to at least one physical address is received, and the requested write access is allowed if the at least one physical address the memory mapping information relates to is within the allowed address range for the process running in or under the supervisor mode.
13. The method according to claim 12 , wherein the memory mapping information is read from a configuration memory region indicated by the second register table, wherein data stored in the configuration memory region represents the allowed address range.
14. The method according to claim 12 , wherein the process running in or under the supervisor mode requests write access to the first register table if a read access to the first register table for mapping a logical physical address to an actual physical address was not successful.
15. The method according to claim 12 , wherein the memory mapping information relates to at least one logical physical address mapped to the at least one actual physical address.
16. The method according to claim 15 , wherein after a write access of the process running in or under the supervisor mode to the first register table has been carried out, a third register table indicating virtual address information for mapping at least one virtual address and at least one actual physical address onto each other is reconfigured to indicate a mapping of a virtual address to the at least one actual physical address the memory mapping information refers to.