IP Library Granted Patent US 8,853,840
Granted Patent B2
US 8,853,840 · App. 13/773,594 · Granted Oct 7, 2014

Semiconductor package with inner and outer leads

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Quick Facts
Patent No.
US 8,853,840
App. No.
13/773,594
Granted
Oct 7, 2014
Kind
B2
Abstract

A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically conductive die mount is molded onto upper surface areas of each inner lead external connection section. A semiconductor die is mounted on the non-electrically conductive die mount and bond wire provide interconnects for selectively electrically connecting bonding pads of the die to the inner lead bonding sections and at least one outer lead bonding section. A mold compound covers the semiconductor die, the bond wires, and the outer and inner lead bonding sections.

Claims (24)

1. A semiconductor die package, comprising:

a plurality of outer leads each having an outer lead external connection section and an outer lead bonding section;

a plurality of inner leads spaced from the outer leads, each of the inner leads having an inner lead external connection section spaced and downset from an inner lead bonding section;

a non-electrically conductive die mount molded onto upper surface areas of each inner lead external connection section and spaced from the plurality of outer leads;

a semiconductor die mounted on the non-electrically conductive die mount;

bond wires selectively electrically connecting bonding pads of the die to at least one inner lead bonding section and at least one outer lead bonding section; and

a mold compound covering at least part of the semiconductor die, the bond wire, and the outer and inner lead bonding sections.

2. The semiconductor die package of claim 1 , wherein the outer lead external connection section is downset from the outer lead bonding section.

3. The semiconductor die package of claim 2 , wherein the inner lead external connection section has a planar inner lead external mounting surface and the outer lead external connection section has a planar outer lead external mounting surface that is co-planar with the planar inner lead external mounting surface.

4. The semiconductor die package of claim 3 , wherein each of the outer leads has an angled section that forms each outer lead downset, the angled section being between the outer lead external connection section and the outer lead bonding section, and wherein the angled section is external to the mold compound.

5. The semiconductor die package of claim 3 , wherein each of the outer leads has an angled section that forms each outer lead downset, the angled section being between the outer lead external connection section and the outer lead bonding section, and wherein the angled section is covered by the mold compound.

6. The semiconductor die package of claim 3 , wherein both the mold compound and the non-electrically conductive die mount form an underside of the package.

7. The semiconductor die package of claim 6 , wherein the planar inner lead external mounting surface protrudes from the underside of the package.

8. The semiconductor die package of claim 6 , wherein the planar inner lead external mounting surface is coplanar with the underside of the package.

9. The semiconductor die package of claim 1 , wherein the outer lead bonding section and inner lead bonding section have coplanar surfaces.

10. The semiconductor die package of claim 1 , wherein the non-electrically conductive die mounts have a continuous surface for supporting the semiconductor die thereon.

11. A semiconductor die package, comprising:

a plurality of outer leads each having an outer lead external connection section and an outer lead bonding section;

a plurality of inner leads spaced from the outer leads, each of the inner leads having an inner lead external connection section spaced and downset from an inner lead bonding section;

a non-electrically conductive die mount molded onto upper surface areas of each inner lead external connection section and spaced from the plurality of outer leads;

a semiconductor die mounted on the non-electrically conductive die mount;

bond wires selectively electrically connecting bonding pads of the die to at least one inner lead bonding section and at least one outer lead bonding section; and

a mold compound covering at least part of the semiconductor die, the bond wire, and the outer and inner lead bonding sections, wherein both the mold compound and the non-electrically conductive die mount form an underside of the package,

wherein the inner lead external connection section has a planar inner lead external mounting surface that is co-planar with a planar outer lead external mounting surface of the outer lead external connection section.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 030445/0737 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030445/0709 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030445/0581 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2013
From: AU, YIN KHENG; HIEW, PEY FANG; YAP, JIA LIN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029853/0970 →