Temperature-based adaptive erase or program parallelism
View Patent ↗A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells.
1. A method comprising:
receiving a signal, wherein the signal indicates a measured temperature; and
performing a memory operation on a group of memory cells that is a subset of a memory block, wherein the number of memory cells of the group is less than a full number of memory cells in the memory block and is based at least in part on the measured temperature, and wherein the memory operation is performed substantially simultaneously on only the group of memory cells, and wherein the performing the memory operation comprises performing a write operation on the group of memory cells.
2. The method of claim 1 , comprising:
providing a voltage to terminals of the group of memory cells.
3. The method of claim 1 , wherein the performing the memory operation comprises writing the memory cells to a first logic state using a voltage of a charge pump.
4. The method of claim 3 , wherein the measured temperature is indicative of a temperature of one or more of the memory cells.
5. The method of claim 1 , wherein the memory cells are arranged in a plurality of pages, each page has a plurality of the memory cells, and the performing the memory operation comprises performing a program operation on a first page among the pages.
6. The method of claim 1 , comprising:
comparing the measured temperature to a first temperature threshold.
7. The method of claim 6 , comprising:
determining that the measured temperature is less than the first temperature threshold; and
in response to the determining that the measured temperature is less than the first temperature threshold, enabling the memory operation by providing a voltage to a set of the memory cells.
8. The method of claim 7 , comprising:
determining that the measured temperature is greater than the first temperature threshold; and
in response to the determining that the measured temperature is greater than the first temperature threshold, enabling a second memory operation by providing the voltage to a first subset of the set of the memory cells, and
after completion of providing the voltage to the first subset of the set of the memory cells, providing the voltage to a second subset of the set of the memory cells.
9. The method of claim 1 , wherein the performing the memory operation comprises performing a program operation on the group of memory cells.
10. The method of claim 1 , wherein the performing the memory operation comprises performing an erase operation on the group of memory cells.
11. The method of claim 1 , comprising:
sequentially erasing groups of the memory cells, wherein each of the groups of memory cells has a same number of memory cells.
12. A method comprising:
receiving a signal, wherein the signal indicates a measured temperature; and
performing a memory operation on a group of memory cells that is a subset of a memory block, wherein the number of memory cells of the group is less than a full number of memory cells in the memory block and is based at least in part on the measured temperature, and wherein the memory operation is performed substantially simultaneously on only the group of memory cells, wherein the performing the memory operation comprises performing a read operation on the group of memory cells.
13. A system comprising:
a plurality of non-volatile memory cells;
a voltage supply configured to provide a voltage for a memory operation;
a temperature sensor configured to measure a temperature; and
a controller coupled to the memory cells, the voltage supply, and the temperature sensor, wherein the controller is configured to
perform a memory operation on a group of memory cells among the memory cells, wherein the number of memory cells of the group is less than a total number of the memory cells and is based at least in part on the temperature, and wherein the memory operation is performed substantially simultaneously on only the group of memory cells,
wherein the voltage supply comprises one or more charge pumps configured to provide the voltage to:
wells of the memory cells; or
gates of the memory cells.
14. The system of claim 13 , wherein:
the controller is configured to couple the voltage supply with groups of memory cells to perform a write to a first logic state on the groups of memory cells;
the controller is configured for determining whether the temperature is above a threshold; and
the controller is configured for selecting, based on a determination that the temperature is above the threshold, only a first subset of the memory cells for a parallel writing operation.
15. The system of claim 13 , wherein the controller is configured to:
select, based at least in part on the temperature, the group of memory cells, and couple the voltage supply with the group of memory cells.
16. The system of claim 13 , wherein the temperature sensor is configured to measure an operating temperature of the memory cells.
17. The system of claim 13 , wherein the controller is configured to couple the voltage supply with selected memory cells among the memory cells based at least in part on:
at least one temperature threshold setting, wherein the temperature threshold setting is a programmable value stored in the controller.
18. A system comprising:
a plurality of non-volatile memory cells;
a voltage supply configured to provide a voltage for a memory operation;
a temperature sensor configured to measure a temperature; and
a controller coupled to the memory cells, the voltage supply, and the temperature sensor, wherein the controller is configured to
perform a memory operation on a group of memory cells among the memory cells, wherein the number of memory cells of the group is less than a total number of the memory cells and is based at least in part on the temperature, and wherein the memory operation is performed substantially simultaneously on only the group of memory cells,
wherein the voltage supply comprises one or more charge pumps configured to provide the voltage to terminals of the memory cells, and the temperature is indicative of a temperature of at least one of the charge pumps.