IP Library Granted Patent US 9,337,670
Granted Patent B2
US 9,337,670 · App. 13/770,170 · Granted May 10, 2016

Circuit and method for battery equalization

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,337,670
App. No.
13/770,170
Granted
May 10, 2016
Kind
B2
Abstract

A battery equalization circuit is provided, including: a positive battery node connecting to a positive node of a battery cell in a battery circuit with a plurality of other battery cells; a negative battery node connected to a negative node of the battery cell; a transformer winding receiving an AC voltage, the transformer winding having an upper transformer node and a tower transformer node; an upper triac connected between the positive battery node and the upper transformer node; a lower triac connected between the negative battery node and the lower transformer node; a control circuit for controlling the upper triac and the lower triac based on a measured cell voltage between the positive battery node and the negative battery node, and a total battery voltage of the battery circuit; and an isolation element connected between the control circuit and a data bus.

Claims (76)

1. A battery equalization circuit, comprising:

a first positive battery node configured to connect to a positive node of a first monitored battery cell contained in a battery circuit that includes a plurality of other battery cells connected in series with the first monitored battery cell;

a first negative battery node configured to connect to a negative node of the first monitored battery cell;

a first transformer winding configured to receive an output voltage of an AC generator, the first transformer winding having a first upper transformer node and a first lower transformer node;

a first upper triac connected between the first positive battery node and the first upper transformer node;

a first lower triac connected between the first negative battery node and the first lower transformer node; and

a multiplexers configured to control the operation of the first upper triac and the first lower triac based on instructions received from a central control unit,

wherein the instructions received from the central control unit are generated based on a first measured cell voltage between the first positive battery node and the first negative battery node, and a total battery voltage of the battery circuit.

2. The battery equalization circuit of claim 1 , wherein the first upper triac and the first lower triac are both optically-coupled triacs.

3. The battery equalization circuit of claim 1 , wherein

the first monitored battery cell and the plurality of other battery cells are all configured to have the same preset voltage, and

wherein the total battery voltage of the battery circuit is determined by measuring a voltage of all of the first monitored battery cell and the plurality of other battery cells arranged in series with each other, and dividing the resulting voltage by a total number of battery cells, including the first monitored battery cell and the plurality of other battery cells.

4. The battery equalization circuit of claim 1 , further comprising

a first analog-to-digital converter connected between the first positive battery node and the first negative battery node, and configured to determine a first analog cell voltage, and to convert the first analog cell voltage into a first digital cell voltage,

wherein the central control circuit uses the first digital cell voltage as the first measured cell voltage.

5. The battery equalization circuit of claim 1 , further comprising

a first switch connected between the first positive node and a voltage-measurement node;

a cluster analog-to-digital converter connected the voltage-measurement node, and configured to determine a first analog cell voltage at the first positive node when the first switch is closed, and to convert the first analog cell voltage into a first digital cell voltage; and

a cluster isolation element for electrically isolating the cluster analog-to-digital converter from the multiplexer,

wherein

the multiplexer controls the operation of the first switch.

6. The battery equalization circuit of claim 1 , further comprising:

a second positive battery node configured to connect to a positive node of a second monitored battery cell selected from the plurality of other battery cells connected in series with the first monitored battery cell;

a second negative battery node configured to connect to a negative node of the second monitored battery cell;

a second transformer winding configured to receive the output voltage of the AC generator, the second transformer winding having a second upper transformer node and a second lower transformer node; and

a triac connected between the second positive battery node and the second upper transformer node,

wherein the multiplexer is further configured to control the operation of the second triac based on further instructions received from a central control unit,

wherein the further instructions received from the central control unit are generated based on a second measured cell voltage between the second positive battery node and the second negative battery node, and the total battery voltage of the battery circuit.

7. The battery equalization circuit of claim 6 , wherein the second triac is an optically-coupled triac.

8. The battery equalization circuit of claim 6 , further comprising

a second analog-to-digital converter connected between the second positive battery node and the second negative battery node, and configured to determine a second analog cell voltage, and to convert the second analog cell voltage into a second digital cell voltage,

wherein the central control circuit uses the second digital cell voltage as the second measured cell voltage.

9. The battery equalization circuit of claim 6 , further comprising

a second switch connected between the second positive node and the voltage-measurement node;

wherein

the cluster analog-to-digital converter is further configured to determine a second analog cell voltage at the second positive node when the second switch is closed, and to convert the second analog cell voltage into a second digital cell voltage, and

the multiplexer controls the operation of the second switch.

10. A battery equalization circuit, comprising:

a primary battery equalization cluster comprising N primary cluster cells;

a central control circuit configured to control the operation of the primary battery equalization cluster, and to provide signals to a data bus; and

an isolation element connected between the control circuit and the data bus, the isolation element being configured to provide electrical isolation between the control circuit and the data bus,

wherein

an i th primary cluster cell further comprises

an i th positive primary battery node configured to connect to a positive node of an i th monitored primary battery cell contained in a primary battery circuit that includes N primary battery cells connected in series with each other,

an i th negative primary battery node configured to connect to a negative node of the i th monitored primary battery cell,

an i th primary transformer winding configured to receive an output voltage of an AC generator, the i th primary transformer winding having an i th upper primary transformer node and an i th lower primary transformer node,

an i th upper primary triac connected between the i th positive primary battery node and the i th upper primary transformer node, and

an i th lower primary triac connected between the i th negative primary battery node and the i th lower primary transformer node,

the control circuit is configured to control the operation of the i th upper primary triac and the i th lower primary triac based on an i th measured primary cell voltage between the i th positive primary battery node and the i th negative primary battery node, and a total primary battery voltage of the primary battery circuit, and

i is an integer index that varies from 1 to N.

11. The battery equalization circuit of claim 10 , further comprising

a secondary battery equalization cluster comprising M secondary cluster cells,

wherein

a j th secondary cluster cell further comprises

a j th positive secondary battery node configured to connect to a positive node of a j th monitored secondary battery cell contained in a secondary battery circuit that includes N secondary battery cells connected in series with each other,

a j th negative secondary battery node configured to connect to a negative node of the j th monitored secondary battery cell,

a j th secondary transformer winding configured to receive the output voltage of the AC generator, the j th secondary transformer winding having a j th upper secondary transformer node and an i th lower secondary transformer node,

a j th upper secondary triac connected between the j th positive secondary battery node and the j th upper secondary transformer node, and

a j th lower secondary triac connected between the j th negative secondary battery node and the j th lower secondary transformer node,

the control circuit is further configured to control the operation of the j th upper secondary triac and the j th lower secondary triac based on a j th measured secondary cell voltage between the j th positive secondary battery node and the j th negative secondary battery node, and a total secondary battery voltage of the secondary battery circuit,

the central control circuit is further configured to provide signals to the data bus, and

j is an integer index that varies from 1 to M.

12. The battery equalization circuit of claim 10 , wherein

an i th primary cluster cell further comprises

an i th primary voltage measuring circuit connected between the i th positive primary battery node and the an i th negative primary battery node, and configured to determine an i th primary analog cell voltage; and

an i th primary analog-to-digital converter configured to convert the i th primary analog cell voltage into an i th primary digital cell voltage,

wherein the control circuit uses the i th primary digital cell voltage as the i th measured primary cell voltage.

13. The battery equalization circuit of claim 10 , further comprising

an i th upper primary switch connected between the i th positive primary battery node and the control circuit; and

an i th lower primary switch connected between the i th negative primary battery node and the control circuit;

wherein

the control circuit controls the operation of the i th upper primary switch and the i th lower primary switch;

the control circuit further comprises

a voltage measuring circuit connected to the i th upper primary switch and the i th lower primary switch, and is configured to measure an i th primary analog cell voltage of the i th monitored primary battery cell when the i th upper primary switch and the i th lower primary switch are both closed, and

an analog-to-digital converter configured to convert the i th primary analog cell voltage into an i th primary digital cell voltage, and

the control circuit uses the i th primary digital cell voltage as the i th measured primary cell voltage.

Assignments (31)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0725 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0704 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0744 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 030445/0737 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030445/0709 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded May 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030445/0581 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2013
From: DROBNIK, JOSEF; BERNOUX, BEATRICE
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 029829/0944 →