Method for forming an integrated circuit having a programmable fuse
View Patent ↗A back-end-of-line thin ion beam deposited fuse ( 204 ) is deposited without etching to connect first and second last metal interconnect structures ( 110, 120 ) formed with last metal layers (LM) in a planar multi-layer interconnect stack to programmably connect separate first and second circuit connected to the first and second last metal interconnect structures.
1. A method for forming an integrated circuit having a programmable fuse, comprising:
providing an integrated circuit structure comprising first and second exposed interconnects electrically connected respectively to first and second circuits in the integrated circuit structure, where the first and second exposed interconnects are physically separated from one another by an interlayer dielectric layer; and
forming a fuse layer on the integrated circuit structure using a localized deposition process to electrically connect the first and second exposed interconnects without applying an etch process to the fuse layer.
2. The method of claim 1 , where providing the integrated circuit structure comprises providing a semiconductor substrate on which is formed a multi-layer interconnect stack formed with a dual damascene fabrication process to define a top planar interconnect stack surface having first and second exposed interconnects comprising copper that are physically separated from one another by a topmost interlayer dielectric layer in the multi- layer interconnect stack.
3. The method of claim 1 , further comprising forming an insulating layer over the fuse layer and integrated circuit structure.
4. The method of claim 1 , further comprising blowing the fuse layer to electrically disconnect the first and second exposed interconnects from one another.
5. The method of claim 1 , where forming the fuse layer comprises using at least one of the group consisting of focused ion beam deposition, ion beam induced deposition, focus ion beam-assisted chemical vapor deposition, selective laser deposition, laser atomic deposition, or electron beam induced deposition to form the fuse layer on the integrated circuit structure.
6. The method of claim 1 , where forming the fuse layer comprises using focused ion beam deposition to form the fuse layer on the integrated circuit structure.
7. The method of claim 1 , where forming the fuse layer comprises forming a thin fuse layer to a thickness of less than approximately 500 Angstroms.
8. The method of claim 1 , where forming the fuse layer comprises forming the fuse layer using focused ion beam deposition of at least one of the group consisting of Ta, Ti, TaN, TiN, Al, Au, Co, Cr, Cu, Fe, Mo, Nb, Ni, Pd, Pt, or W.
9. The method of claim 1 , where forming the fuse layer comprises forming a focused ion beam deposited fuse layer to overlap with the first and second exposed interconnects without forming an overhang portion that also extends past the first and second exposed interconnects.
10. The method of claim 1 , where providing the integrated circuit structure comprises providing a semiconductor substrate on which is formed a multi-layer interconnect stack formed with a dual damascene fabrication process to define a planar interconnect stack surface having first and second exposed interconnects physically separated from one another by an interlayer dielectric layer in the multi-layer interconnect stack.
11. The method of claim 1 , further comprising blowing the fuse layer to electrically disconnect the first and second exposed interconnects from one another by selectively applying a programming laser or excessive current to the fuse layer to cause electro- mechanical conductor failure and/or thermal melting of the fuse layer form an open or blown fuse.
12. A method of forming an integrated circuit device, comprising using a localized deposition process to form a programmable thin conductive fuse layer on first and second exposed interconnects of the integrated circuit device to electrically connect the first and second exposed interconnects without applying an etch process to the programmable thin conductive fuse layer, where the first and second exposed interconnects are respectively coupled to first and second circuits in the integrated circuit device.
13. The method of claim 12 , further comprising providing the integrated circuit device with a multi-layer interconnect stack formed with a dual damascene fabrication process to define a top planar interconnect stack surface having first and second exposed damascene interconnects comprising copper that are physically separated from one another by a topmost interlayer dielectric layer in the multi-layer interconnect stack.
14. The method of claim 12 , further comprising forming an insulating layer over the programmable thin conductive fuse layer.
15. The method of claim 12 , further comprising blowing the programmable thin conductive fuse layer to electrically disconnect the first and second exposed damascene interconnects from one another.
16. The method of claim 12 , where using the localized deposition process comprises using at least one of the group consisting of focused ion beam deposition, ion beam induced deposition, focus ion beam-assisted chemical vapor deposition, selective laser deposition, laser atomic deposition, or electron beam induced deposition to form the programmable thin conductive fuse layer.
17. The method of claim 12 , where forming the programmable thin conductive fuse layer comprises forming a fuse layer to a thickness of less than approximately 500 Angstroms.
18. The method of claim 12 , where forming the programmable thin conductive fuse layer comprises using focused ion beam deposition of at least one of the group consisting of Ta, Ti, TaN, TiN, Al, Au, Co, Cr, Cu, Fe, Mo, Nb, Ni, Pd, Pt, or W.
19. The method of claim 12 , where forming the programmable thin conductive fuse layer comprises forming a focused ion beam deposited fuse layer to overlap with the first and second exposed damascene interconnects without forming an overhang portion that also extends beyond the first and second exposed damascene interconnects.