Non-volatile memory (NVM) and logic integration
View Patent ↗A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer in an NVM region and a polysilicon dummy gate is formed over a second thermally-grown oxygen-containing layer in a logic region. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first and second thermally-grown oxygen-containing layers are formed. The second thermally-grown oxygen-containing layer and the dummy gate are replaced by a metal gate and a high-k dielectric. The logic transistor is protected while the NVM cell is then formed including forming a charge storage layer.
1. A method of forming an NVM cell and a logic transistor using a semiconductor substrate, comprising:
in a non-volatile memory (NVM) region, forming over the semiconductor substrate a first thermally-grown oxygen-containing layer, a select gate of a first material, and a first dielectric layer, wherein the select gate is on the first thermally-grown oxygen-containing layer, a top surface of the first dielectric layer is substantially aligned with a top surface of the select gate, and the first dielectric layer has a first opening in which the select gate is present in the first opening;
in a logic region, forming over the semiconductor substrate a second thermally-grown oxygen-containing layer and a dummy gate of the first material and, after forming the first thermally-grown oxygen-containing layer and the select gate, forming a source and a drain in the semiconductor substrate, and a second dielectric layer, wherein the dummy gate is on the second thermally-grown oxygen-containing layer, a top surface of the second dielectric layer is substantially aligned with a top surface of the dummy gate, and the second dielectric layer has a second opening in which the dummy gate is present in the second opening;
replacing the second thermally-grown oxygen-containing layer with a high-k gate dielectric and the dummy gate with a metal gate;
forming a hard mask over the NVM region and the logic region;
removing the first dielectric layer in the NVM region while leaving the second dielectric layer in the logic region, wherein the forming the hard mask is performed prior to the removing the first dielectric layer;
forming a charge storage layer over the NVM region including over the select gate;
forming a conductive layer over the charge storage layer;
etching the conductive layer to form a control gate; and
etching the charge storage layer to leave a remaining portion of the charge storage layer aligned to the control gate.
2. The method of claim 1 , wherein:
the forming the charge storage layer is further characterized by forming nanocrystals over the second dielectric layer and the metal gate; and
the etching the charge storage layer is further characterized by removing the charge storage layer over the second dielectric layer and the metal gate.
3. The method of claim 2 , wherein:
the step of forming the conductive layer is further characterized by forming the conductive layer over the logic region; and
the step of etching the conductive layer is further characterized by removing the conductive layer over the logic region.
4. The method of claim 1 , wherein the forming the first dielectric layer and forming the second dielectric layer are further characterized as forming the first dielectric and the second dielectric layers simultaneously of a same material.
5. The method of claim 1 , further comprising forming a first silicide region on the source and a second silicide region on the drain of the logic transistor prior to the forming of the second dielectric layer.
6. The method of claim 5 , further comprising:
forming a sidewall spacer around the metal gate prior to the forming the second dielectric layer.
7. The method of claim 6 , further comprising:
forming a liner around the metal gate prior to the forming the sidewall spacer.
8. The method of claim 1 , further comprising removing the hard mask from over the NVM region while leaving the hard mask over the logic region prior to removing the first dielectric layer.
9. The method of claim 1 , wherein the first material comprises polysilicon.
10. The method of claim 1 , wherein:
the forming the metal gate comprises forming a stack comprising a work-function-setting metal on the high-k gate dielectric and a top metal over the work-function-setting metal.
11. The method of claim 1 , wherein the forming the charge storage layer comprises:
forming a base dielectric layer;
forming nanocrystals on the base dielectric layer; and
forming a fill dielectric layer around and over the nanocrystals.
12. The method of claim 1 , wherein the forming the charge storage layer comprises forming a layer of silicon nitride.
13. A method of forming a non-volatile memory (NVM) cell and a logic transistor using a semiconductor substrate, comprising:
forming a polysilicon select gate over a first thermally-grown oxygen-containing layer and a dummy gate over a second thermally-grown oxygen-containing layer;
after forming the first and second thermally-grown oxygen-containing layers, forming a sidewall spacer around the dummy gate;
forming source/drains in the substrate adjacent to the dummy gate;
forming a dielectric layer around the polysilicon select gate and the dummy gate wherein a top surface of the dielectric layer is substantially aligned with a top surface of the polysilicon select gate and a top surface of the dummy gate;
removing the dummy gate;
replacing the second thermally-grown oxygen-containing layer with a high-k dielectric;
replacing the dummy gate with a metal gate;
forming a hard mask over the metal gate;
removing the dielectric layer from around the polysilicon select gate while leaving the dielectric layer around the metal gate, wherein the forming the hard mask is performed prior to the removing the dielectric layer;
forming a charge storage layer over the semiconductor substrate;
forming a conductive layer over the charge storage layer;
etching the conductive layer to form a control gate over a portion of the charge storage layer and removing the conductive layer from over the hard mask;
etching the charge storage layer to leave a portion of the charge storage layer under the control gate and removing the charge storage layer from over the hard mask; and
forming second source/drains in the substrate adjacent to the select gate and control gate.
14. The method of claim 13 , further comprising removing the hard mask.
15. The method of claim 14 further comprising siliciding the second source/drains prior to the removing the hard mask.
16. The method of claim 15 further comprising siliciding the first source/drains prior to the forming the dielectric layer.
17. The method of claim 13 , wherein the replacing the dummy gate further comprises forming a work-function-setting layer on the high-k dielectric and forming a metal fill over the work-function-setting layer.
18. A method, comprising:
forming a polysilicon select gate of a non-volatile memory (NVM) cell on a first thermally-grown oxygen-containing layer in an NVM region of a semiconductor substrate and a polysilicon dummy gate on a second thermally-grown oxygen-containing layer in a logic region of the semiconductor substrate;
forming source/drains adjacent the polysilicon dummy gate;
forming a sidewall spacer around the polysilicon dummy gate and siliciding the source/drains adjacent the sidewall spacer;
forming a dielectric having a top surface that is substantially aligned to a top surface of the polysilicon select gate and a top surface of the polysilicon dummy gate;
replacing the polysilicon dummy gate and the second thermally-grown oxygen-containing layer with a metal gate and a high-k dielectric layer, respectively;
forming a hard mask over the logic region;
removing the dielectric from around the polysilicon select gate, wherein the forming the hard mask is performed prior to the removing the dielectric from around the polysilicon select gate;
forming a charge storage layer over the logic region and the NVM region;
forming a conductive layer over the logic region and the NVM region;
etching the conductive layer over the NVM region to form a control gate over the charge storage layer and removing the conductive layer from the logic region;
etching the charge storage layer to leave the charge storage layer under and aligned with the control gate and to remove the charge storage layer over the logic region; and
forming source/drain regions in the substrate in the NVM region adjacent to the control gate and to the polysilicon select gate.
19. The method of claim 18 further comprising:
siliciding the source/drain regions in the substrate in the NVM region; and
removing the hard mask after the siliciding the source/drain regions in the substrate in the NVM region.