Test control point insertion and X-bounding for logic built-in self-test (LBIST) using observation circuitry
Test control point insertion and x-bounding for Logic Built-In Self-Test (LBIST) using observation circuitry. In some embodiments, LBIST circuitry may include a plurality of test control circuits coupled to a scan chain of a Circuit Under Test (CUT), and a plurality of observation circuits coupled to the test control circuits, each of the plurality of observation circuits including one or more latch devices configured to drive a respective one of the plurality of test control circuits. In other embodiments, a method of testing an integrated circuit may include issuing an instruction that a plurality of observation circuits and a plurality of input/output (I/O) control circuits within the integrated circuit enter a test mode, and providing, one or more test patterns to a selected one or more of a plurality of scan chains within the integrated circuit and to each of the plurality of observation circuits.
1. Logic Built-In Self-Test (LBIST) circuitry, comprising:
a plurality of test control circuits coupled to a plurality of scan chains; and
a plurality of observation circuits coupled to the plurality of test control circuits, wherein each of the plurality of observation circuits includes a latch or flip-flop configured to apply at least a portion of a test pattern to a respective one of the plurality of test control circuits, wherein each of the plurality of test control circuits is configured to provide at least a portion of the test pattern to a respective one of the plurality of scan chains, and wherein the latch or flip-flop in each of the plurality of observation circuits is configured to capture at least a portion of a test result of a respective one of the plurality of scan chains.
2. The LBIST circuitry of claim 1 , further comprising an LBIST controller operably coupled to the plurality of test control circuits and to the plurality of observation circuits, the LBIST controller configured to provide a test signal to each of the plurality of observation circuits and to each of the plurality of test control circuits, the test signal configured to place the plurality of observation circuits and the plurality of test control circuits in a test state.
3. The LBIST circuitry of claim 2 , further comprising a test pattern generator operably coupled to the LBIST controller and to the plurality of observation circuits, the test pattern generator configured to provide the one or more test patterns to the plurality of observation circuits when the plurality of observation circuits and the plurality of test control circuits are in the test state.
4. The LBIST circuitry of claim 3 , wherein the latch or flip-flop in each of the plurality of observation circuits is coupled to two or more the plurality of test control circuits, wherein each of the two or more of the plurality of test control circuits does not have any flip-flops or latches, and wherein each of the two or more of the plurality of test control circuits is configured to provide the test pattern to the respective one of the plurality of scan chains while the two or more of the plurality of test control circuits are in the test state.
5. The LBIST circuitry of claim 4 , further comprising an output response analyzer operably coupled to the LBIST controller and to the plurality of observation circuits, the output response analyzer configured to receive one or more response patterns from the plurality of observation circuits and to identify one or more signatures corresponding to the one or more response patterns.
6. The LBIST circuitry of claim 1 , further comprising a plurality of input/output (I/O) control circuits operably coupled to the plurality of observation circuits, wherein each of the plurality of I/O control circuits does not have any flip-flop or latch devices, and wherein the latches or flip-flops within the plurality of observation circuits are further configured to drive respective ones of the I/O control circuits.
7. The LBIST circuitry of claim 6 , further comprising an LBIST controller operably coupled to the plurality of I/O control circuits and to the plurality of observation circuits, the LBIST controller configured to provide a test signal to each of the plurality of observation circuits and to each of the plurality of I/O control circuits, the test signal configured to place the observation and I/O control circuits in a test state.
8. A method comprising:
issuing, by a Logic Built-In Self-Test (LBIST) circuit within an integrated circuit, a signal configured to instruct a plurality of observation circuits and a plurality of input/output (I/O) control circuits within the integrated circuit to enter a test mode, wherein each of the plurality of observation circuits includes a flip-flop configured to provide at least a portion of a test pattern to a respective one of the plurality of I/O control circuits, wherein each of the flip-flops is further configured to store a response to the respective portion of the test pattern received from the respective one of the plurality of I/O circuit, and wherein each of the plurality of I/O control circuits does not have any flip-flops; and
providing the test pattern by the LBIST circuit to the plurality of observation circuits.
9. The method of claim 8 , wherein the signal is applied to a multiplexer in each of the plurality of I/O control circuits, the signal configured to cause each multiplexer to select the test pattern instead of an input external to the integrated circuit.
10. The method of claim 8 , further comprising applying, by the observation circuits, the test pattern to the plurality of I/O control circuits, wherein the test pattern, applied by the plurality of observation circuits, is configured to place the plurality of I/O control circuits in one or more known states.
11. The method of claim 10 , further comprising receiving, by the LBIST circuit, responses from the plurality of observation circuits and identifying one or more signatures corresponding to the response.
12. The method of claim 8 , further comprising providing, by the LBIST circuit, a test signal to each of a plurality of test control circuits, wherein the test signal is configured to place the test control circuits in the test mode, wherein each of the plurality of test control circuits is configured to provide a respective portion of the test pattern received directly from a respective one of the flip-flops to a portion of the integrated circuit when two or more of the plurality of test control circuits are in a test state.
13. A device, comprising:
an electronic circuit; and
a Logic Built-In Self-Test (LBIST) circuit operably integrated into the electronic circuit, the LBIST circuit configured to provide a test signal to test control circuits, input/output (I/O) control circuits, and observation circuits within the electronic circuit, wherein the test control circuits are configured to apply logic values to points internal to the electronic circuit as part of a test procedure, wherein the I/O control circuits are configured to perform x-bounding operations as part of the test procedure, wherein the observation circuits are configured to capture results of the testing procedure, wherein the test signal is configured to put the test control circuits, I/O control circuits, and observation circuits in a test state, wherein the LBIST circuit is configured to provide a test sequence to the observation circuits, wherein each given one of the test control circuits is configured to provide at least a portion of the test sequence received from a respective one of the observation circuits to a portion of the electronic circuit while the given one of the test control circuits is in the test state, wherein each of the observation circuits includes a latch or flip-flop configured to receive at least a portion of the test sequence and to subsequently receive a given result of the portion of the test sequence propagated through the portion of the electronic circuit, and wherein the LBIST circuit is configured to determine whether a signature generated based upon the given result indicates that the electronic circuit is operating properly.
14. The device of claim 13 , wherein the & latch or flip-flop is configured to provide the test sequence directly to a logic gate circuit within the test control circuit without any intermediate latches or flip-flops during a shifting operation.
15. The device of claim 14 , wherein each of the latches or flip-flops is configured to receive a respective result of a respective portion of the test sequence propagated through a respective portion of the electronic circuit through one or more scan chains during a capture operation.
16. The device of claim 15 , wherein the one or more scan chains operate with different clocks, and wherein the LBIST circuit is configured to operate with a clock having a period longer than any clock with which the one or more scan chains operate.